tag: gate all around

Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)
By Technical Paper Link - 15 Feb, 2026 - Comments: 0

Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)
By Technical Paper Link - 03 Jan, 2026 - Comments: 0

A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips
By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control
By Jiangtao Hu - 09 Dec, 2025 - Comments: 0

AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, manufacturers are rapidly accelerating advanced logic and DRAM development. Chief among these innovations: gate-all-around (GAA) logic transistor and vertical gate (VG) DRAM, two device architectures that promise higher performance, improved power efficiency, and greater scalabil... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography
By Travis Brist - 23 Oct, 2025 - Comments: 0

The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

AI Pushes High-End Mobile From SoCs To Multi-Die
By Liz Allan - 08 Jul, 2025 - Comments: 0

Advanced packaging is becoming a key differentiator for the high end of the mobile phone market, enabling higher performance, more flexibility, and faster time to market than systems on chip. Monolithic SoCs likely will remain the technology of choice for low-end and midrange mobile devices because of their form factor, proven record, and lower cost. But multi-die assemblies provide more fle... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
By Technical Paper Link - 28 Jun, 2025 - Comments: 0

A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)
By Technical Paper Link - 24 Jun, 2025 - Comments: 0

A new technical paper titled "Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes" was published by researchers at Sungkyunkwan University and Alsemy Inc. "This paper explores the design and optimization of multi-Nanosheet Field-Effect Transistors (mNS-FETs) employing a Transition Metal Dichalcogenide (TMDC) channel, specifically MoS2, for the 0.7 nm technology node u... » read more

Research Bits: Mar. 25
By Jesse Allen - 25 Mar, 2025 - Comments: 0

2D materials in 3D transistors Researchers at the University of California Santa Barbara investigated 3D gate-all-around (GAA) transistors made using 2D semiconductors. They considered three different approaches to channel stacking: nano-sheet FETs, nano-fork FETs, and nano-plate FETs. The nano-plate FET architecture, which exploits lateral stacking of 2D layers, was found to maximize the g... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

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