Reimagining PVT Monitoring IP For Advanced Node GAA Process

On-chip sensing technology is shifting towards digital techniques.


As process technology continues to evolve, so must design tools and the IP that support them. One example of an industry evolution is on the PVT monitoring IP side. The process, voltage, and temperature (PVT) monitors embedded within chips provide feedback on silicon status at every stage of the lifecycle, including mission use in the field. The data gathered from the monitors enables benefits such as early prediction of impending chip failures and tracking of trends across a “fleet” of chips deployed worldwide.

Now, let’s delve into the fast-evolving world of semiconductor technology and explore the recent transition to Gate-All-Around (GAA) transistors. These novel devices are poised to revolutionize chip design and address the limitations of their predecessors. Moore’s law has been the most accurate forecasting model known to date and is now entering the Angstrom (Å) age. The semiconductor ecosystem will have to adapt for supporting chips designed and fabricated in advanced node processes.

From finFETs to GAA: A brief history

When finFETs made their debut at the 22 nm node, they marked a significant departure from traditional planar transistors. The fin structure, surrounded by gates on three sides, offered superior channel control. However, as we push toward the 5 nm and 3 nm nodes, finFETs face challenges related to drive current, electrostatic control, and leakage.

Enter GAA transistors. These innovative structures allow the gate to encircle the channel from all sides, enabling continued scaling. Let’s explore the two key aspects of GAA transistors:

  1. Nanosheets: Early GAA devices utilize vertically stacked nanosheets. These sheets consist of separate horizontal layers, each enveloped by gate materials. Unlike finFETs, where higher current necessitates multiple side-by-side fins, GAA transistors achieve increased current-carrying capacity by stacking a few nanosheets vertically. This flexibility in sizing allows transistors to meet specific performance requirements.
  2. Channel Control: GAA transistors offer improved channel control compared to finFETs. By wrapping the gate around the channels, they mitigate short-channel effects and leakage through the uncontacted bottom of the device. As we scale down, nanosheet dimensions will continue to evolve, eventually resembling nanowires.

Fig. 1: FinFET vs GAA structure. (Source: Applied Materials)

Benefits and challenges

The benefits of GAA transistors make a compelling case for migration to this superior approach for advanced nodes. For a successful transition, the traditional process of circuit design must also evolve. The good news for digital designers is that GAA transistors are well suited for digital circuits. Their improved channel control and scalability allow for efficient logic gates and memory cells. Adoption of GAA will enable digital circuits to benefit from enhanced performance and reduced power consumption.

The benefits are less clear for analog designers. While GAA transistors primarily target digital applications, they can also be adapted for analog designs. However, achieving the same level of precision as in digital circuits may pose challenges. Analog designers will need to explore novel techniques to harness the benefits of GAA transistors. For example, bipolar devices like BJT are likely to become less prevalent. These are used today primarily in mixed-signal applications.

Changes in design are inevitable but clearly worthwhile for the benefits achieved. It is important to recognize that successful adoption of GAA also requires modifications to the manufacturing process. While the concept of nanosheets is straightforward, their fabrication presents several new manufacturing challenges. These include precise structuring and the need for novel materials to achieve the desired power, performance, area, and cost (PPAC) scaling targets.

Adapting PVT monitoring IP to support GAA

The design of PVT monitoring IP has to undergo a major rethink to stay ahead of the curve and adapt to the advent of the GAA transistor. The current lack of characterized bipolar junction transistors (BJT) and thick oxide FET are the major drivers for this adaptation and are causing a shift in sensing technology to move towards digital techniques. Simply put, adapt and evolve or become irrelevant fast.

The digital techniques have the added benefit of not only a smaller area/footprint but also help eliminate the need for protecting sensed signals from the effect of noise/crosstalk needed for analog signals. Things such as analog wire shielding will no longer be needed with a move towards a digital paradigm.

System-on-chip (SoC) and IP vendors will need to find innovative ways of maintaining analog-like accuracy, and that’s going to be where the differentiation will lie.

This move towards digital sensing will be of great benefit to the industry with not only reduction in power and faster conversion rates, but also making implementation of PVT monitoring IP easier, allowing the flexibility for more remote sensors to be placed closer together to the intended sense points. In the case of temperature sensors, with sense points placed closer to hot spots the effects of the temperature gradient is minimized; and, with multiple sense points, triangulation can be used to improve accuracy further. It’s a win-win from all aspects.


The GAA transistor revolution is underway, promising to overcome finFET limitations and advance Moore’s Law. Most industry observers believe that following this path is inevitable for all chip, IP, and SoC developers and foundries. Manufacturing processes and equipment will evolve as needed, especially as the industry embraces true 3D devices. All chip design engineers should brace themselves for a new era in semiconductor technology. Learn about Synopsys SLM PVT Monitor IP.

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