A lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction to reduce alignment-solution errors.
AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this study, we use overlay data from 510 x 515mm panel test vehicles to identify zone-level correctables and apply in-exposure pre-compensation. The approach reduces overlay errors in high-volume manufacturing, improving overlay by 38.2%. The methodology generalizes to ultra-high-density fan-out and 2.5D/3D packaging, providing a practical path to sustain overlay yield for next-generation AICS.
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