Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography


AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

AI-Empowered Analog IC Sizing Methods (Univ. of Glasgow Et Al.)


A new technical paper titled "From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing" was published by researchers at University of Glasgow, Mediatek, The University of Edinburgh, Magics Technologies NV, University of Sevilla and Georgia Institute of Technology. Abstract "This paper presents a comprehensive, design-insight-based compa... » read more

Moving Past “It Works” — Intelligent Optimization Is the Key to PCB Excellence


In the fast-evolving field of electronic systems design, engineers are under increasing pressure to deliver innovative, high-performance products within ever-shrinking development cycles. Traditional methods—relying on intuition, trial-and-error testing, and even basic simulation—struggle to keep pace with the growing complexity of modern systems. Nowhere is this more evident than in printe... » read more

Simulation Closes Gap Between Chip Design Optimization And Manufacturability


Simulation is playing an increasingly critical and central role throughout the design-through-manufacturing flow, fusing together everything from design to manufacturing and test in order to reduce the number and cost of silicon respins. The sheer density of modern chips, combined with advanced packaging techniques like 3D stacking and heterogeneous integration, has made iterative physical p... » read more

Goal-Driven AI


For many, the long-term dream for AI within EDA is the ability to define a set of goals and tell the computer to go design it for them. A short while later, an optimized design will pop out. All of today's EDA tools will remain hidden, if they even exist at all. You would only be limited by your imagination. But we also know that AI is not to be trusted today, especially when millions of dol... » read more

Accelerated Optimization With IC Compiler II


Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

Designing A Better Clock Network


Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

E/E Architecture Synthesis: Challenges and Technologies


ACADEMIC PAPER Abstract "In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded pow... » read more

Why Comparing Processors Is So Difficult


Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems


Abstract: "More than Moore technologies can be supported by system-level diversification enabled by chiplet-based integrated systems within multichip modules (MCMs) and silicon interposer-based 2.5-D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at the ... » read more

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