Goal-Driven AI


For many, the long-term dream for AI within EDA is the ability to define a set of goals and tell the computer to go design it for them. A short while later, an optimized design will pop out. All of today's EDA tools will remain hidden, if they even exist at all. You would only be limited by your imagination. But we also know that AI is not to be trusted today, especially when millions of dol... » read more

Accelerated Optimization With IC Compiler II


Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

Designing A Better Clock Network


Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

E/E Architecture Synthesis: Challenges and Technologies


ACADEMIC PAPER Abstract "In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded pow... » read more

Why Comparing Processors Is So Difficult


Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems


Abstract: "More than Moore technologies can be supported by system-level diversification enabled by chiplet-based integrated systems within multichip modules (MCMs) and silicon interposer-based 2.5-D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at the ... » read more

Intelligent Agents for the Optimization of Atomic Layer Deposition


"Atomic layer deposition (ALD) is a highly controllable thin film synthesis approach with applications in computing, energy, and separations. The flexibility of ALD means that it can access a massive chemical catalogue; however, this chemical and process diversity results in significant challenges in determining processing parameters that result in stable and uniform film growth with minimal pr... » read more

Dealing With Two Very Different Sides Of 5G


Semiconductor Engineering sat down to discuss 5G reliability with Anthony Lord, director of RF product marketing at FormFactor; Noam Brousard, system vice president at proteanTecs; Andre van de Geijn, business development manager at yieldHUB; and David Hall, head of semiconductor marketing at National Instruments. What follows are excerpts of that conversation. To view part one of this discussi... » read more

Optimizing What Exactly?


You can't optimize something without understanding it. While we inherently understand what this means, we are often too busy implementing something to stop and think about it. Some people may not even be sure what it is that they should be optimizing and that makes it very difficult to know if you have been successful. This was a key message delivered by Professor David Patterson at the Embedde... » read more

Challenges At 3/2nm


David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

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