Spectral Tunability For Accuracy, Robustness And Resilience


In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups a... » read more

High-Volume Manufacturing Device Overlay Process Control


By Honggoo Leea, Sangjun Hana, Jaeson Wooa, DongYoung Leea, ChangRock Songa, Hoyoung Heob, Irina Brinsterb, DongSub Choic, John C. Robinsonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Corp., 8834 N. Capital of Texas Hwy, Austin, TX 78759 cKLA-Tencor Korea, Starplaza bldg.., 53 Metapolis-ro, Hwasung City, Gyeonggi-do, Korea Abstract ... » read more

What’s In A Node?


In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

Overlay Challenges On The Rise


The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink. Both ASML and KLA-Tencor recently introduced new [getkc id="307" kc_name="overlay"] metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/... » read more

Improving Optical Overlay And Measurement


By Adam Ge and Shimon Levi Patterning challenges for the semiconductor industry are growing as the number of multi-patterned layers being used in the 10nm and beyond nodes increase. Patterning requires highly accurate overlay which has always been an issue, but with the added complexities of multi-patterning, smaller dimensions and subsequent tightening overlay error budget, it is now a majo... » read more

Inside Lithography And Masks


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="IMEC"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cov... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Changing Direction In Chip Design


Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

Accuracy In Optical Overlay Metrology


By Barak Bringoltz, Tal Marciano, Tal Yaziv, Yaron DeLeeuw, Dana Klein, Yoel Feler, Ido Adam, Evgeni Gurevich, Noga Sella, Ze’ev Lindenfeld, Tom Leviant, Lilach Saltoun, Eltsafon Ashwal, Dror Alumot and Yuval Lamhot, Xindong Gao, James Manka, Bryan Chen, and Mark Wagner. Abstract In this paper we discuss the mechanism by which process variations determine the overlay accuracy of optical m... » read more

Inside Advanced Patterning


Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at [getentity id="22817" e_name="Applied Materials"], sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion. SE: From your standpoint, what are the big... » read more

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