Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)

Chiplets will require increasingly larger packages and more redistribution layers.


By John Chang, with Corey Shay, James Webb, and Timothy Chang

For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based increasingly on heterogeneous integration.

But while heterogeneous integration promises more functionality, faster data transfer, and lower power consumption, these chiplet combinations, with different functionalities and nodes, will require increasingly larger packages, with sizes at 75mm x 75mm, 150mm x 150mm, or even larger.

To further complicate matters, these packages will also feature elevated numbers of redistribution layers, in some cases as high as 24 layers. And with each of those layers, the threat of a single killer defect, which would effectively ruin an entire package, increases. As such, the ability to maintain high yields becomes increasingly difficult.

In our previous blog, “Heterogeneous Integration: Exposing Large Panels With Fewer Shots,” we discussed how an extremely large exposure field, fine-resolution lithography system eliminated the need for stitching the large packages needed for heterogeneous integration. As detailed, a large-field stepper with an exposure size of 250mm x 250mm can fully expose a 510mm x 515mm panel in only four shots, as opposed to current steppers with an exposure field of 59mm x 59mm. For those tools, it takes 64 shots to reach full exposure. And where it concerns line/space capabilities, the extremely large exposure field, fine-resolution lithography system is able to achieve a line/space of 3µm, while offering a depth of focus up to 60µm. In addition, such a system demonstrates the ability to reach an overlay number of less than 1µm, an aggressive benchmark for future advanced packaging applications.

In this blog, we’ll focus on how the successful application of an extremely large exposure field, fine-resolution lithography system can identify overlay error terms and substrate distortion components in an advanced integrated circuit substrate (AICS) process for heterogenous integration and compensate for these process inducted errors to achieve good overlay.

To demonstrate this, we used the system’s intra-field and global correction capabilities. By analyzing metrology data collected by the lithography system, we identified error terms and distortions in the test vehicles. In addition, we identified anamorphic and third order radial distortion in a full-panel model; however, the error terms change when fitting in a quadrant of the panel.

Furthermore, we found various substrate distortion errors in each quadrant of the panel, indicating that a global solution correction cannot fully correct for all distortion errors on its own; a unique correction is needed. By doing this, we were able to achieve successful overlay results. Analysis also revealed that if substrate distortion errors are not corrected properly, the overlay error vector could be 20µm or higher (figures 1 and 2).

Fig. 1: Test overlay results with proper corrections and method. The unit of measurement is µm.

Fig. 2: Overlay results using improper corrections and method. These numbers indicate that improper corrections and method were applied during exposure, resulting in poor overlay. The unit of measurement is µm.

To correct these substrate distortion errors, we used a lithography software tool, which resulted in better overlay results. The software tool provided corrections for each quadrant of the panel. This zone solution correction was applied during exposure of the substrate to enable better overlay results. According to the overlay data, reasonable overlay results can be achieved by using zone solution corrections. However, better overlay numbers are to be expected when using yield predictions derived by the proprietary algorithm.

The alignment marks on the test vehicle were created by a laser drilling system. Due to the limitations of the laser drilling system, we observed lower mark capture accuracy and poor laser mark shape control, leading to an alignment solution error. This alignment solution error can result in overlay errors, even though the lithography system or metrology system recognizes the alignment marks. Based on this finding, an additional offset may be needed to address this issue.

To address alignment solution errors, we used a proprietary algorithm, which predicted the overlay results with additional compensation. Using this algorithm, we analyzed the correctable terms based on current overlay errors. Following the removal of correctable errors, we were able to reduce overlay errors by 4µm or more.

As a result of heterogeneous integration and high-performance computing requirements, resolution will move toward 1µm in fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) and 3µm in AICS. In addition, the budget for overlay is getting tighter due to the fine line/space resolution requirements, which will require a more complicated alignment solution to meet the overlay specification requirements.

Based on the data we obtained, an extremely large exposure field, fine-resolution lithography system can achieve 3µm resolution and is able to achieve a mean overlay of +3 sigma less than 1µm. The data also confirms that an extremely large exposure field, fine-resolution lithography system can successfully identify distortion components in a 510mm x 515mm panel and provide accurate corrections to achieve good overlay. According to our analysis, we are confident that proper error and distortion corrections, coupled with the zone correction solution are key to achieving the best overlay numbers in AICS manufacturing.

The ability to address these AICS manufacturing challenges will further assist the industry in meeting the requirements demanded by next-level technologies targeting high-performance computing, artificial intelligence, and data centers. And with tools like the lithography system discussed here at the ready, manufactures will be able to successfully reach the new performance milestones enabled by panel-level packaging and heterogenous integration as we move further into the More than Moore era.

Corey Shay is a senior applications engineer at Onto Innovation.

James Webb is a director of technology at Onto Innovation.

Timothy Chang is a senior director of applications at Onto Innovation.

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