tag: packaging

Creating A Moore’s Law For AI Scaling
By Laura Peters - 24 Jun, 2026 - Comments: 0

Key Takeaways: AI scalability will require full-stack co-optimization, not just bigger data centers. AI workloads require a 10X compute efficiency gain over 10 years, making collaboration across algorithms, architectures, devices, packaging, and communication fabrics essential to deliver a 10X improvement in compute efficiency over the next decade.  Edge AI chips are moving to leadi... » read more

Packaging Technologies Redefine AI And HPC Scalability Limits At ECTC 2026
By Lori Scott - 05 Jun, 2026 - Comments: 0

The 2026 IEEE Electronic Components and Technology Conference (ECTC) showcased how advanced packaging can redefine the scalability limits of artificial intelligence (AI) and high-performance computing (HPC). Across 20 technical papers, Intel Foundry engineers and collaborators highlighted breakthrough innovations — from Embedded Multi-die Interconnect Bridge-T (EMIB-T) enabling large multi-d... » read more

Wafer-Scale vs. Chiplets: The New War? Part 1
By Nandan Nayampally - 28 May, 2026 - Comments: 0

Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

Home Win: Challenging The Traditional Semiconductor Manufacturing Model
By Chris Rand - 12 May, 2026 - Comments: 0

Across Europe, many of us have grown accustomed to a model where semiconductor products, subassemblies and components are sourced from the Far East almost by default. The rationale has always been clear: significantly lower labor and manufacturing costs made offshore supply the most commercially viable option. Yet, while this approach has long been convenient, it has never been without compromi... » read more

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging
By KyungSu Kim - 16 Apr, 2026 - Comments: 0

The relentless march of semiconductor scaling continues to reshape the packaging landscape, driven by Moore’s Law and the demand for higher performance in increasingly compact form factors [1]. Over the past two decades transistor density has increased exponentially, with leading-edge processes now achieving densities exceeding 100 million transistors per square millimeter. Certain applica... » read more

Research Bits: Mar. 31
By Jesse Allen - 31 Mar, 2026 - Comments: 0

2D hard mask material Researchers from Penn State University and University of Chemistry and Technology Prague propose using the 2D material chromium oxychloride (CrOCl) as a hard mask, because its layered structure is resistant to plasma etching and enables it to be an effective mask at smaller thicknesses. “This 2D material is like lasagna. It’s a layer-by-layer structure,” said Zih... » read more

Quantifying The Impact Of Gravity On Strip Warpage Across Assembly Stages
By Nathan Whitchurch - 19 Mar, 2026 - Comments: 0

The mechanical behavior of electronic packages is an important consideration at each stage of the assembly process. Many packages are assembled in strip format, making strip warpage a critical challenge for manufacturability and yield. Accurate simulations for strip warpage are an effective tool to determine what factors cause large warpages and to explore solutions before assembly. In these si... » read more

How AI Is Changing Computing And Why Testing Is Critical
By Jeorge Hurtarte - 10 Mar, 2026 - Comments: 0

Artificial intelligence (AI) is transforming industries, enhancing our daily lives, and improving efficiency and decision-making, but its need for compute processing power is growing at an astonishing rate, doubling every three months (Figure 1). To maintain this pace, the semiconductor industry is moving beyond traditional chip development – it has entered the era of heterogeneous chiplets i... » read more

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