Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies


In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

Current Characterization Of Various Cu RDL Designs In Wafer Level Packages (WLP)


Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and widths of 5-20 µm are used for high current sourcing. In this case, the temperature of the Cu RDL metal line increases due to the Joule heat generated when current passes through the metal line. If a... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System


High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity


By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging


With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Powering Next-Generation Insightful Design


The Ansys team is gearing up for an exciting time at DAC this week, where we’ll be sharing a whole new way of visualizing physical phenomena in 3D-IC designs, powered by NVIDIA Omniverse, a platform for developing OpenUSD and RTX-enabled 3D applications and workflows. Please attend our Exhibitor Forum session so we can show you the valuable design insights you can gain by interactively viewin... » read more

The Race To Glass Substrates


The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve. Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. But ... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design


Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

Using Deep Learning ADC For Defect Classification For Automatic Defect Inspection


In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of... » read more

Package Integrated Vapor Chamber Heat Spreaders


With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

← Older posts