tag: packaging

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity
By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging
By Heejun Jang - 23 Jul, 2024 - Comments: 0

With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Powering Next-Generation Insightful Design
By Sara Louie - 24 Jun, 2024 - Comments: 0

The Ansys team is gearing up for an exciting time at DAC this week, where we’ll be sharing a whole new way of visualizing physical phenomena in 3D-IC designs, powered by NVIDIA Omniverse, a platform for developing OpenUSD and RTX-enabled 3D applications and workflows. Please attend our Exhibitor Forum session so we can show you the valuable design insights you can gain by interactively viewin... » read more

The Race To Glass Substrates
By Gregory Haley - 29 May, 2024 - Comments: 4

The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve. Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. But ... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design
By Ruben Fuentes - 23 May, 2024 - Comments: 0

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

Using Deep Learning ADC For Defect Classification For Automatic Defect Inspection
By Onto Innovation - 14 May, 2024 - Comments: 0

In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of... » read more

Package Integrated Vapor Chamber Heat Spreaders
By Sanghyuk Kim - 21 Mar, 2024 - Comments: 0

With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging
By JiHye Kwon - 18 Jan, 2024 - Comments: 0

The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

High Performance, Multi-Chip Leadframe Package With Internal Connections
By DaeYoung Park - 19 Dec, 2023 - Comments: 0

For high performance applications, demand for highly integrated packages has increased. This is due to the highly integrated package’s electrical performance advantages of reduction of interchip distance (delay), high density I/O counts for multi-function and small form factor [1-3]. With the increasing importance of highly integrated packages, the need for improved thermal management is also... » read more

Fluid Dispensing For Packaging Today’s Devices
By Nordson Test And Inspection - 12 Dec, 2023 - Comments: 0

Fluid dispensing systems are evolving in order to address the challenges that system-in-package (SiP) and micromechanical systems (MEMS) packages face, especially in regard to tight geometries and assembly processes. These packages, used in smartphones, have become more miniaturized, and as a result, have created added value in the market. However, they include a variety of small dies or dev... » read more

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