How Overlay Keeps Pace With EUV Patterning

As tolerances tighten and density increases, these tools help ensure sufficient yield.


Overlay metrology tools improve accuracy while delivering acceptable throughput, addressing competing requirements in increasingly complex devices.

In a race that never ends, on-product overlay tolerances for leading-edge devices are shrinking rapidly. They are in the single-digit nanometer range for the 3nm generation (22nm metal pitch) devices. New overlay targets, machine learning, and improved optical overlay systems help speed necessary checks to ensure yield at 5nm and 3nm nodes.

In lithography, overlay accuracy has become one of the most critical yield limiters. Overlay control is all about ensuring precise alignment between the features on one mask layers with the one below. For leading-edge nodes like 5nm, overlay tolerance — typically 30% of feature size — must be kept below a few nanometers. “Leading memory and logic customers are running 2 to 2.5nm on-product overlay,” said Jan Mulkens, an ASML fellow.

A typical device might have 50 or more mask levels, only some of which are critical and require EUV (13.5nm), while non-critical layers use ArF (193nm) exposure. Key advances at the EUV scanner, inspection, and algorithm levels work together to deliver tight overlay control and more yielding wafers.

Some of the trends in overlay include:

  • Movement to longer wavelengths (near IR) to align layers through new hard masks that are opaque to optical wavelengths;
  • Overlay targets that better mimic the device;
  • Increased metrology sampling, and
  • ML algorithms to crunch masses of data faster for better inline results.

In addition, some inspection tool hardware changes such as chuck improvements help counter bowing effects.

EUV tool-level developments
Obtaining good overlay starts with lithography. The goal of a scanner is to print tiny features with fine resolution, as well as to precisely align them. To accomplish that, tiny alignment marks are placed on both a wafer and a photomask. In the scanner, a wafer stage and reticle stage aligns the appropriate marks with one another. The exposure per reticle is scanned, then it steps, aligns, and exposes the next chip on the wafer until it is fully patterned.

Fig. 1: Overlay is measured after lithography patterning (after develop inspection) and after features are etched (AEI). Source: KLA

Fig. 1: Overlay is measured after lithography patterning (after develop inspection) and after features are etched (AEI). Source: KLA

In the litho cell, overlay is measured on fairly similar optical metrology systems, one positioned after the layer is patterned (after develop inspection), and the second after etch (AEI).

“We’re finding that memory customers seem to be moving faster towards an increased use of after etch inspection, rather than in the past when it was a more static thing,” said Jim Kavanagh, head of application engineering at ASML. “The need to make sure they capture the variances in the etch-induced overlay fingerprint is critical, especially in 3D NAND channel holes where variances from wafer-to-wafer, lot-to-lot, and chamber-to-chamber can be significant. In logic, because they have multiple feature types, it’s harder to anchor an overlay feature that is representative of the device, so they do more at ADI.”

In the fab, two to four overlay metrology tools may be used for every EUV lithography system. ASML, KLA, and Applied Materials provide CD and overlay metrology tools optimized for the two overlay steps. Both image-based overlay (IBO) methods are used, as well as diffraction-based overlay (DBO, a.k.a. scatterometry), and some systems combine the two techniques. The overlay target has top and bottom gratings, so that when imaged at an angle and detected, it creates signal differences that correspond with the edge-to-edge differences in images.

Feedback between ADI and AEI, as well as input from the scanner’s sensors, are used to make overlay corrections. For instance, linear corrections in the x and y directions are made, as well as rotational corrections. But with advanced lithography and shrinking features, the scanner now implements higher-order corrections to reach incredible accuracy requirements.

“During scanning, the scanner can correct for translation and rotational errors, but it also can handle higher-order corrections,” said Chris Mack, CTO of Fractilia. Overlay targets in the scribeline around die provide the basis for overlay measurements. “The higher-order errors are things that are more than just what’s going on in the four corners — such as variation in the middle of devices — so the scanning motion of the wafer and mask can implement those corrections. The more measurement points you have, the more exacting you can make the movements.”

Edge placement errors
The budget for overlay keeps shrinking, not only because feature sizes are getting smaller and mask levels are increasing, but because of stochastic effects. The stochastics also impact overlay and CD measurements.

“In the old days, CD non-uniformity and overlay were the main contributors to what we call edge-placement errors (EPE). But with scaling, and especially double patterning, there are multiple components of EPE,” said Mack. Total EPE is essentially the difference between what engineers intended to print on the wafer and the actual features that are fabricated. In order of importance these include four components — CD uniformity stochastics (line-width and line-edge roughness), OPC CD errors, and global CD uniformity errors.

“The largest source of EPE is from stochastics, so more emphasis is being placed on reducing overlay errors because stochastics are so difficult to control,” Mack said. “In fact, stochastics are expected to account for 50% of EPEs at 3nm. So what does all this mean for overlay control? Fabs still need to build devices with small edge placement error. But now they have less than half the budget for CD uniformity and overlay. So the requirements on overlay and CD uniformity are shrinking even faster than before.”

Others point to similar issues. “With continued shrinking of EPE budgets for the 5nm node, overlay elements of the EPE budget shrink the fastest, with higher within-field variation,” said Andrew Cross, director of Process Control Solutions at KLA.

This leads to higher optical overlay sampling, improved overlay measurement techniques, and introduction of SEM-based overlay measurements at AEI and ADI. Optical metrology tools use wavelengths in the 500 to 650nm range, which is optimal for many process layers and conditions, but now long-wavelength (900nm) lasers can image through opaque hard masks, especially used in NAND but also DRAM, for particular layers. The result is more flexible metrology systems to meet the greatest number of needs.

Overlay measurement, calibration
Pattern placement is first checked after the photoresist is developed, and if overlay is unacceptable, the wafer(s) can be reworked. In high-volume manufacturing, fabs may monitor CD uniformity and overlay on select (6) wafers per lot and every lot or perhaps every other lot. ASML’s approach to overlay monitoring includes compiling and crunching great volumes of data.

ASML’s Mulkens explains the components that go into overlay. “Customers take the diffraction measurements from the target in the scribe line. Then, of course, we need to know how that measured overlay on targets compares to the overlay on device. We call that device overlay. Typically, the optical targets have a pitch of several hundred nanometers, and the devices are in the order of 20 to 30 nanometer pitch. So there is a metrology to device (MTD) offset, which customers measure and calibrate. Then, of course, you’re still not there because there may be very local errors with EUV, stochastics. People use e-beam systems to measure these very local errors, which may be on the order of several nanometers. With the CD and overlay errors you may end up with 4 to 5nm overlay and placement error in total.”

The SEM captures local stochastics, which together with the overlay measurement are used to determine overlay corrections and CD corrections on the scanner.

Fig. 2: Feedforward and feedback of scanner and metrology data to correct for overlay and CD errors. Source: ASML

Fig. 2: Feedforward and feedback of scanner and metrology data to correct for overlay and CD errors. Source: ASML

When it comes to new technology ramps and correlation of optical measurement systems, e-beam imaging is widely used. Only e-beam tools can detect the surface characteristics at the angstrom level by detecting signals from backscattered electrons. In production, while some manufacturers talk about the need to use more e-beam measurements in-line, the slower throughput still restricts tool usage.

Because SEMs are increasing used for CD SEM measurements, it begs the question whether CD SEM and local CDU measurements can be combined in one system.

“They tend to have different voltage requirements and other differences, so while there may be some cases where overlay and CD SEM can be combined, it isn’t typical,” said Mack. “[Using physics-based models,] we are developing the ability to make both overlay and stochastic measurements like roughness and all the components that lead to an edge placement error simultaneously. We believe that’s the direction the industry is going in, given the right algorithms.”

Target modifications
Overlay measurements rely on measurements made on targets — features in the scribe-line or selectively, in-device. The targets are film stacks with a grating using looser dimensions than the device itself (hundreds of nanometers), tailored to the layer to capture in-device overlay.

Target designs play a fundamental role in overlay measurement precision and accuracy, but are also subject to size restraints in the scribe line. This is causing some movement to smaller, more detailed targets (4 to 8µm per side). Traditional targets were bar-in-bar or box-in-box designs, 25 x 25µm, but a more sensitive version is shown in figure 3.

Fig. 3:  Target design improves the capture of overlay error. Source: SPIE

Fig. 3:  Target design improves the capture of overlay error. Source: SPIE

Shlomit Katz, application development team lead at KLA, described recent changes in overlay target design such as greater use of Moiré effect targets. Using overlay interference patterns produced by overlaying but slightly offset patterns, Moire effect can be displaced, rotated, or have slightly different pitch, creating phase-induced interference. New targets for NAND and DRAM “are proving to be robust to both symmetric and asymmetric process variation, improve the contrast through wavelength and also improve the total measurement uncertainty,” said Katz.[1]

On-wafer measurements in the scanner before exposure help achieve high-quality exposure, but they also can reveal critical information that feeds process control loops. For instance, wafer topography maps detect local overlay errors due to focus spots that might be missed by overlay sampling.

ASML and STMicroelectronics recently provided a glimpse of what next-generation overlay control might look like in fabs using overlay-based computational corrections. By combining physical modeling with machine learning, they showed that scanner measurements can be used to predict the overlay performance on wafers or lots that are not measured by metrology to detect potential excursions.[2]

“In order to get the accuracy in the scanner, we have our inbuilt sensors, alignment sensor and the leveling sensor, they measure every wafer, and they measure the wafer at a very dense level. As a matter of fact, this is one of the few data sets the customer may have characterizing high spatial fingerprints for each wafer. So we derive some algorithms and couple these sensors with the measurements outside of the scanner with the overlay equipment. When you do this correctly, the customers can minimize the amount of measurements outside the scanner, or they may use that data to up-sample the density of measurements outside the scanner,” said ASML’s Mulkens.

Density is driving a number of changes. “One of the key trends we’re seeing, coupled with the need for higher precision and higher accuracy, is greater sampling to capture the fingerprints across the wafer, but just as important also to capture the variation between wafer and lots,” Mulkens said. “We see that both when we’re measuring ADI with an optical target-based metrology tool and after etch. And then, of course, with the e-beam tool, people are looking at local placement.”

Applied Materials also talks about greater sampling on wafers to improve accuracy and detect across-wafer variation or fingerprints. For instance, the company’s e-beam tool is designed to measure edge placement and CDs at multiple levels simultaneously. For a robust process, correlation between ADI and AEI is fundamental to overlay process control (see figure 4).

Fig. 4: Correlation between after develop and after etch inspection for overlay control. Source: Applied Materials

Fig. 4: Correlation between after develop and after etch inspection for overlay control. Source: Applied Materials

While overlay control for the most advanced devices strives to feed back data to the scanner more quickly to compensate for errors in-line, the next generation of tools, high-NA EUV, will come will its own challenges. It uses an anamorphic lens, supporting 8X magnification in one direction, 4X in the other. So field size is reduced by half and the results of two masks are stitched together on the wafer.

“With anamorphic optics, the 6-inch mask leads to what we call half fields,” said Mulkens. “Now, when you print critical layers on the high-NA system and less critical layers on the lower NA system, you need to be able to match the half fields to the full fields, and vice versa. In order to come up with matching algorithms, we do non-concentric matching, and that will be the big overlay innovation when it comes to high-NA.”

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Finding, Predicting EUV Stochastic Defects
Unusual effects at 5/3nm, including fewer defects with double patterning.

High-NA EUV May Be Closer Than It Appears
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[1] S. Katz, Y. Grauer and E. Megged, “Optical Overlay Metrology Trends in Advanced Nodes,” Proceedings SPIE Metrology, Inspection, and Process Control, May 2022,

[2] L. van Dijk, et. al., “Computational Overlay as Enabler for Enhanced On-Product Overlay Control,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), May 2022,



guest says:

14 nm half-pitch?

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