Matching Between Simulations and Measurements As a Key Driver for Reliable Overlay Target Design


By S. Lozenko, B. Schulz, L. Fuerst, C. Hartig, and M. Ruhm of GlobalFoundries and T. Shapoval, G. Ben-Dov, Z. Lindenfeld,  R. Haupt, and R. Wang of KLA-Tencor Abstract Numerical simulation of overlay metrology targets has become a de-facto standard in advanced technology nodes. While appropriate simulation software is widely available in the industry alongside with metrics that allow sel... » read more

In-Cell Overlay Metrology By Using Optical Metrology Tool


By Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyong Kima, Jieun Lee, DongYoung Leea, Eungryong Oh, and Ahlin Choi of SK Hynix, and Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John C. Robinson of KLA-Tencor Abstract Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced s... » read more

Spectral Tunability For Accuracy, Robustness And Resilience


In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups a... » read more

FinFET Metrology Challenges Grow


Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

Overlay Challenges On The Rise


The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink. Both ASML and KLA-Tencor recently introduced new [getkc id="307" kc_name="overlay"] metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/... » read more

Accuracy In Optical Overlay Metrology


By Barak Bringoltz, Tal Marciano, Tal Yaziv, Yaron DeLeeuw, Dana Klein, Yoel Feler, Ido Adam, Evgeni Gurevich, Noga Sella, Ze’ev Lindenfeld, Tom Leviant, Lilach Saltoun, Eltsafon Ashwal, Dror Alumot and Yuval Lamhot, Xindong Gao, James Manka, Bryan Chen, and Mark Wagner. Abstract In this paper we discuss the mechanism by which process variations determine the overlay accuracy of optical m... » read more

Can We Measure Next-Gen FinFETs?


After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

Measuring Atoms And Beyond


David Seiler, chief of the Engineering Physics Division within the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST), sat down with Semiconductor Engineering to discuss the current and future directions of metrology. NIST, a physical science laboratory, is part of the U.S. Department of Commerce. What follows are excerpts of that conversation. SE: W... » read more

Measuring FinFETs Will Get Harder


The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Flash Dance For Inspection And Metrology


Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

← Older posts