Using Sensor Data To Improve Yield And Uptime


Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

Lithography Challenges For Fan-out


Higher density fan-out packages are moving toward more complex structures with finer routing layers, all of which requires more capable lithography equipment and other tools. The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these critical dimensions (CDs), fan-outs will provide better per... » read more

AI In Chip Manufacturing


Ira Leventhal, New Concept Product Initiative vice president at Advantest, talks with Semiconductor Engineering about using analysis and deep learning to make test more efficient and more effective. https://youtu.be/3VVG4JVnjHo » read more

AI Training Chips


Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering about how to architect an AI training chip, how different processing elements are used to accelerate training algorithms, and how to achieve improved performance. https://youtu.be/4cnBCX-9jlk     See other tech talk videos here. » read more

Variability In Chip Manufacturing


Brewer Science’s Jim Korich talks about how to deal with variability in processes and why consistency in materials is so important at advanced nodes. https://youtu.be/U1KkUmtmqpE » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm


Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Process Corner Explosion


The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

3D NAND Flash Wars Begin


3D NAND suppliers are gearing up for a new battle amid a period of price and competitive pressures, racing each other to the next technology generations. Competition is intensifying as a new player enters the 3D NAND market—China’s Yangtze Memory Technologies Co. (YMTC). Backed by billions of dollars in funding from the Chinese government, YMTC recently introduced its first 3D NAND techn... » read more

Estimating MOSFET Leakage From Low-Cost, Low-Resolution Fast Parametric Test


A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient tran... » read more

Defect Reduction At 7/5nm


Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

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