tag: yield

Memory On Logic: The Good And Bad
By Brian Bailey - 11 Apr, 2024 - Comments: 0

The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Partnership To Improve Semiconductor Quality And Yield
By Eli Roth - 08 Feb, 2024 - Comments: 0

By Eran Rousseau (NI) and Eli Roth (Teradyne) The semiconductor industry is notorious for its high production costs and the critical importance of maintaining impeccable product quality. As technology advances and consumer expectations rise, semiconductor companies face constant pressure to meet these cost and quality goals while also delivering cutting-edge products. Traditionally, the s... » read more

Yield Tracking In RDL
By Ed Sperling - 07 Feb, 2024 - Comments: 0

Yield is a much bigger issue when it comes to panel-level packages, which may contain up to 24 RDL layers. Just finding the defects is a massive challenge, let alone understanding how they will impact the entire device. Many of these advanced packages are being used in data centers for generative AI, and killer defects caused by bridges and opens can cause serious problems. What happens, for in... » read more

ML-Assisted IC Test Binning With Real-Time Prediction At The Edge
By PDF Solutions - 07 Feb, 2024 - Comments: 0

IC Test is a critical part of semiconductor manufacturing and proper die binning and material disposition has an important impact on the overall yield and on the process monitoring and failure mode diagnostics. Edge analytics are becoming an increasingly important aspect of die disposition. By intercepting parts in real-time at the wafer test step, we can save downstream processing needs. In th... » read more

Fabs Begin Ramping Up Machine Learning
By Anne Meixner - 19 Dec, 2023 - Comments: 0

Fabs are beginning to deploy machine learning models to drill deep into complex processes, leveraging both vast compute power and significant advances in ML. All of this is necessary as dimensions shrink and complexity increases with new materials and structures, processes, and packaging options, and as demand for reliability increases. Building robust models requires training the algorithms... » read more

Improving Semiconductor Yield Using Large Area Analysis
By Jacky Huang - 19 Dec, 2023 - Comments: 0

Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Total Overlay With Multiple RDLs
By Ed Sperling - 13 Nov, 2023 - Comments: 0

As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

Rebalancing Test And Yield In IC Manufacturing
By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Installing Yield Software Early In A Ramp Up
By Dieter Rathei - 10 Oct, 2023 - Comments: 0

In 1999, the White Oak Semiconductor Fab in Richmond, VA, was awarded the prestigious “Top Fab of the Year” (yes, that actually existed – proof attached!) by the leading semiconductor magazine of the time. Back then, I was a young engineer on the ramp up team and I recall that the reason we were chosen for the award was the incredibly short time in which we were able to ramp up production... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy