tag: yield

Effective UX/UI Is A Critical Link Between AI Insights And Yield Improvement
By Keira Lei - 09 Jun, 2026 - Comments: 0

The semiconductor industry is undergoing a fundamental shift in how data is generated, analyzed, and acted upon thanks to the integration of AI into process control flows. As AI becomes more deeply integrated into the manufacturing process, its value is increasingly determined not by data-driven decision making alone, but by how effectively its outputs are delivered, interpreted, and acted upon... » read more

Complete End-To-End Closed-Loop Product Yield Ramp And Learning
By Guy Cortez - 12 May, 2026 - Comments: 0

By Guy Cortez and Maheshwaran Jothi Yield ramp has always been a concern in semiconductor manufacturing: systems companies need confidence that devices meet quality targets before shipment, and chipmakers need to reach yield entitlement quickly to control cost and supply. While this has never been easy, advanced nodes are raising the bar again. First, designs are larger and more heterogen... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

When Semiconductor Materials Misbehave
By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication
By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

Maximize Your Revenue With High-Speed Test Performance Optimization
By Jesse Ko - 10 Mar, 2026 - Comments: 0

In today’s competitive semiconductor market, revenue growth is often associated with design innovation, process advancements, or packaging breakthroughs. However, a powerful and frequently overlooked revenue lever lies much closer to production: high-speed test performance optimization. Test variability—particularly at high frequencies—can significantly influence product binning, yield... » read more

Detecting Chemical Variability At Advanced Nodes
By Gregory Haley - 10 Mar, 2026 - Comments: 2

Key Takeaways Yield loss is increasingly driven by molecular variability in thin films, interfaces, and contamination rather than visible defects. Reliability issues often appear first as parametric drift or margin erosion under workload and thermal stress. Detection requires correlating molecular metrology, embedded electrical telemetry, and AI-driven wafer inspection. As s... » read more

Chiplets 2026: Where Are We Today?
By Barry Pangrle - 24 Feb, 2026 - Comments: 0

Jim Handy of Objective Analysis and Jawad Nasrullah from Palo Alto Electron kicked off last week's Chiplet Summit with predictions about where the chiplet market is headed and why chiplets are needed to accelerate AI. Handy noted that in the 1990s, multi-chip modules (MCMs) led to mid-'90s multi-chip packages (MCPs), and then progressed to NAND flash stacking, stacked die, big chips (e.g., X... » read more

When Cleaning Chips Isn’t Clean Enough
By Gregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy