Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography


AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

Semiconductor Metrology: IMMSE For The Rapid ID of Defective Chips (Samsung)


A new technical paper titled "Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology" was published by researchers at Samsung. Abstract "We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of ... » read more

Advanced Part Average Testing For Chips


Part average testing, one of the mainstays of semiconductor test, is becoming much more challenging at advanced nodes and in multi-die assemblies. In the past, PAT produced a Gaussian distribution that made it relatively simple to find outliers. That's no longer the case. Advanced packaging and leading-edge designs have unique attributes that determine which rules apply, such as the thickness o... » read more

2025-Product Design Enhancement With Test Structures For Non-Contact Detection Of Yield Detractors


Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction... » read more

Leveraging Machine Learning in Semiconductor Yield Analysis


Searching through wafer maps looking for spatial patterns is not only a very time-consuming task to be done manually, it’s also prone to human oversight and error, and nearly impossible in a large fab where there are thousands of wafers a day being processed. We developed a tool that applies automatic spatial pattern detection algorithms using ML, parametrizing pattern recognition and clas... » read more

Using BDA To to Predict SAQP Pitch Walk


A new technical paper titled "Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning" was published by researchers at IBM TJ Watson Research Center and Rensselaer Polytechnic Institute. Find the technical paper here. Published November 2022.  Open Access. Scott D. Halle, Derren N. Dunn, Allen H. Gabor, Max O. Bloomfield, and Mark Sh... » read more

Next Steps For Improving Yield


Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

Test Connections Clean Up With Real-Time Maintenance


Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more