Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026

Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets tighten further, high‑numerical aperture (NA) EUV is becoming increasingly important for extending single‑patterning capability and controlling variability.

There are many challenges associated with such advanced lithography. With high‑NA EUV’s reduced field size, large designs may require two stitched exposures. This makes stitch‑aware design rules and stitch‑friendly physical design increasingly important, and it drives new requirements for optical proximity correction (OPC) and other resolution enhancement technology (RET) related mask synthesis steps to maintain pattern fidelity through process and mask variation.

As a result, lithography and patterning remain areas of active research and rapid evolution. Two recent industry events offered the chance to hear from experts about the latest advances in these fields. Synopsys Lithography VIP Symposium was held on February 23 in San Jose, California, with a focus on how graphics processing unit (GPU) acceleration, artificial intelligence (AI)/machine learning (ML), and emerging automation are reshaping computational lithography and mask synthesis to improve yield, raise engineering efficiency, and reduce turnaround time. The event brought together senior industry leaders for high-level presentations and concluded with a panel discussion on “AI/ML in Mask Synthesis:  Hype vs. Reality” to separate practical adoption from speculation.

This symposium was co-located with SPIE Advanced Lithography + Patterning 2026, held in San Jose on February 22-26. SPIE is the international society for optics and photonics, and this was the 50^th anniversary of their annual event. Leading experts and innovators gathered to hear research, challenges, and breakthroughs in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications. Synopsys was a major contributor to this conference, with a dozen technical papers and presentations listed during the week.

One Synopsys invited paper that drew strong interest was “Machine learning enhanced optical proximity correction modeling for high-NA EUV lithography,” presented by Zhiru Yu. High-NA EUV lithography poses challenges due to anamorphic optics and the need for highly accurate OPC models. The work reported in this presentation investigated OPC modeling for an 18 nm pitch line-space array with a 9 nm after-development inspection critical dimension (ADI-CD), requiring sub-1 nm CD error across all variation sources.

Because high‑NA EUV introduces anisotropic optics and tight error budgets, the work emphasized the essential need for accurate topographical mask modeling and consideration of background reflection effects. To close remaining model gaps, the team integrated a machine learning convolutional neural network (CNN) with compact modeling to capture localized proximity behavior. This achieved the required ADI-CD prediction fidelity for advanced high-NA EUV nodes without overfitting. The validation results for the stitching region and black-border contexts successfully predicted the contours, accounting for long range effects (including metal oxide resist (MOR)-related long-range behavior) while maintaining a small shift variance.

Thuc Dam of Synopsys began his presentation on “Co-optimized double exposure stitching with ILT to maximize high-NA EUV process window” by noting that stitched high-NA EUV patterns require new extensions to OPC and RET in order to ensure sufficient patterning control through process and mask variations. Simultaneous co‑optimization of the two stitched exposures and their corresponding masks using inverse lithography technology (ILT) can significantly improve the overall process window for high‑NA EUV stitched patterning.

This talk showed how co-optimization can improve resolution, process windows, and edge placement error (EPE), while also addressing practical constraints such as mask rule checks and design rule restrictions of real design patterns in advanced high-NA EUV processes with stitched exposure fields. The examples highlighted how ILT co-optimization can reduce overlay sensitivity in the stitch region and mitigate failure modes that emerge first at stitched boundaries.

A paper on “Rigorous modeling and repair of EUV multilayer defects,” co-authored with Intel, was presented by Intel’s Joseph M. Rodriguez. Buried multilayer (ML) defects in EUV masks continue to pose a significant challenge to imaging fidelity and yield in 0.33 NA EUV lithography. The work used a rigorous S-Litho model to simulate how buried multilayer defects affect the aerial image across defect depth, position, and feature type. The model captured full 3D electromagnetic interactions, enabling accurate prediction of defect printability and through-focus behavior.

Building on this predictive capability, the team developed a simulation-guided defect repair flow that provided mask repair recommendations to compensate for the reflectivity loss due to ML defects.  The repair strategy was explicitly constrained to be compatible with the available mask‑repair tool capabilities.  Experimental results from production EUV masks demonstrated first‑pass repair success using this approach and measurements confirmed that the post‑repair aerial‑image CD closely matched the defect‑free reference, with the worst CD deltas less than 6%.

Synopsys’ Vito Dai presented “Near-optimal sampling of physical design layout regions based on rigorous pattern coverage,” addressing a persistent practical problem:  how to sample enough layout sites for metrology, model building, and ML training without missing critical infrequently encountered patterns—or wasting effort on redundant samples. The work introduced pattern coverage, a rigorous metric derived from range patterns and demonstrated a coverage‑based sampling algorithm that reduced oversampling while ensuring coverage across diverse layouts.

This presentation showed how to address both concerns in a rigorous and quantifiable way, using a novel computational methodology based on range patterns. These enabled precise counting of the patterns and sub-patterns in any sample layout region. This pattern coverage metric quantified the pattern content of sampled layout regions, including whether any pattern has been missed or over-sampled. A near-optimal coverage-based-sampling algorithm ensured that no patterns are missed and minimizes over-sampling. Its effectiveness was validated across a wide range of layouts.

This post has highlighted only a subset of the many Synopsys advances presented during SPIE 2026, but a consistent direction was clear: as patterning pushes into tighter error budgets, progress increasingly depends on compute‑enabled modeling, stitching‑ready methodologies, and robust metrology and verification workflows. As an industry leader and partner, Synopsys will continue to work with customers and collaborators to deliver new innovative solutions and share the exciting results at future conferences.  We look forward to connecting with you at next year’s SPIE Advanced Lithography + Patterning—please stop by the Synopsys booth to see what’s new. If you’d like to discuss our latest developments in more detail, contact us at [email protected] or visit https://www.synopsys.com/manufacturing.html.