tag: patterning

Semiconductor Device Manufacturing Process Challenges And Opportunities
By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

Novel Assist Layers To Enhance EUV Lithography Performance Of Photoresists On Different Substrates
By Brewer Science - 16 Aug, 2023 - Comments: 0

In EUV lithography, good resist patterning requires an assist layer beneath it to provide adhesion to prevent pattern collapse of small features and allow for higher aspect ratios. In addition, future EUV high numerical aperture (NA) is expected to require a decrease in thickness from the overall patterning stack. In this study, we are exploring a fundamentally new approach to developing an alt... » read more

Direct Synthesis of Planar (2D) Micro and Nanopatterned Epitaxial Graphene on SiC
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Direct synthesis of nanopatterned epitaxial graphene on silicon carbide” was published by researchers at University of Technology Sydney, Ludwig-Maxilimians Universität München, Monash University, and Imperial College London. Abstract: "This article introduces a straightforward approach for the direct synthesis of transfer-free, nanopatterned epitaxial graphene... » read more

Nanoimprint Finally Finds Its Footing
By Gregory Haley - 20 Apr, 2023 - Comments: 2

Nanoimprint lithography, which for decades has trailed behind traditional optical lithography, is emerging as the technology of choice for the rapidly growing photonics and biotech chips markets. First introduced in the mid-1990s, nanoimprint lithography (NIL) has consistently been touted as a lower-cost alternative to traditional optical lithography. Even today, NIL potentially is capable o... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Pathfinding By Process Window Modeling
By Coventor - 19 Oct, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D®. The ... » read more

Underlayer Optimization Method For EUV Lithography
By Brewer Science - 21 Jul, 2021 - Comments: 0

Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern c... » read more

Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning
By TEL - 17 Dec, 2020 - Comments: 0

We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Challenges At 3/2nm
By Ed Sperling - 15 Sep, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Advanced Materials For High-Temperature Process Integration
By James Lamb - 16 Jul, 2020 - Comments: 0

From the last several lithography nodes, in the 14 to 10nm range, to the latest nodes, in the 7 to 5nm range, the requirements for patterning and image transfer materials have increased dramatically. One of the key pinch points is the tradeoff between planarization and the high-temperature stability required from carbon films used in patterning and post-patterning process integration. Patter... » read more

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