tag: ESD

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

What To Do About Electrostatic Discharge
By Ed Sperling - 20 Nov, 2023 - Comments: 0

Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

ESD Co-Design For 224G And 112G SerDes In FinFET Technologies
By Synopsys - 25 Oct, 2023 - Comments: 0

In addressing the challenges of enhancing ESD resilience for high-speed SerDes interfaces, it's crucial to ensure the implementation of appropriate ESD protection measures. This is particularly vital during the device's lifecycle from the conclusion of silicon wafer processing to system assembly, a phase during which electronic devices are highly susceptible to Electrostatic Discharge (ESD) dam... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies
By Synopsys - 07 Jun, 2023 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Ensuring ESD Protection Verification With Industry-Standard Checks
By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

Are You Paying Proper Attention To Your ESD Design Windows?
By Derong Yan - 10 Nov, 2022 - Comments: 0

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

Complete Reliability Verification For Multiple-Power-Domain Designs
By Siemens EDA - 09 Nov, 2022 - Comments: 0

With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

2.5/3D IC Reliability Verification Has Come A Long Way
By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Design & Implementation of CMOS Interface Circuits For high-Voltage Automotive Signals, with Fully Integrated Clamps
By Technical Paper Link - 30 May, 2022 - Comments: 0

Research paper titled "CMOS Interface Circuits for High-Voltage Automotive Signals" from University of Parma and Silis s.r.l. Abstract "The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of ele... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis
By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2023 SMG   |  Terms of Service  |  Privacy Policy