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Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?


Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs


While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

The Shortest Path Deception


When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug


Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

Week In Review: Manufacturing, Test


OEMs For some time, the automotive industry has suffered due to chip shortages in the market. And the chip shortages are spreading into other markets. In the latest news, GM plans to idle key truck plants amid chip shortages, according to a report from Bloomberg. “GM said eight of its 14 North American assembly plants will experience shutdowns this month because of chip shortages, includi... » read more

Debugging Point-to-Point Resistance Using Contribution By Layer In IC Validator PERC


PERC Point-to-point resistance (P2P resistance) functionality is a crucial EDA technology to enable complex P2P effective resistance measurement along ESD paths in automation for foundry qualified ESD/Latch-up checker or in-house custom checker. This technology is applied to the entire chip, block, and IP designs on cell or transistor level layout database. Since the ESD path count could grow t... » read more

Managing Wafer Retest


Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Meeting Automotive Functional Safety Requirements With GPIOs


Automotive OEMs are building advanced driver assistance systems (ADAS) to improve safety. ADAS systems must meet stringent performance, power, and cost requirements, so the system-on-chips (SoCs) that make up ADAS and passenger safety systems integrate advanced protocols and are built on leading edge finFET process technologies. Designers of this new class of ADAS SoCs are challenged to meet IS... » read more

Many Chiplet Challenges Ahead


Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

Evaluate ESD Robustness With Cell-Based P2P/CD Verification


Detecting and verifying an ESD structure can be challenging for designers without specialized ESD experience. The Calibre PERC reliability platform offers cell-based P2P and CD checks that can be used to quickly, accurately, and easily evaluate ESD robustness without the need for advanced ESD expertise. To read more, click here. » read more

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