KAN: Kolmogorov Arnold Networks: An Alternative To MLPs (MIT, CalTech, et al.)


A new technical paper titled "KAN: Kolmogorov-Arnold Networks" was published by researchers at MIT, CalTech, Northeastern University and The NSF Institute for Artificial Intelligence and Fundamental Interactions. Abstract: "Inspired by the Kolmogorov-Arnold representation theorem, we propose Kolmogorov-Arnold Networks (KANs) as promising alternatives to Multi-Layer Perceptrons (MLPs). While... » read more

Datacenter Chipmaker Achieves Double-Digit Power Reduction with Next-Gen Voltage Scaling


The Customer A fabless chipmaker making 5nm networking chips for datacenters. The Challenge High power consumption due to excessive voltage guard-bands What You'll Discover: Learn how the customer safely decreased the voltage from 650 mV to an average of 608 mV, resulting in a 12.5% dynamic power reduction. This significant optimization helped the chipmaker stand out as a low-pow... » read more

MCU Changes At The Edge


Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ... » read more

Integrating Energy Efficiency Considerations Into Your Design From The Beginning


Data center networking is responsible for consuming about 1% of the global electricity supply. With the advent and integration of AI into various sectors, the pressure on both hardware and software infrastructures, necessitated by neural networks and extensive language models, is expected to increase significantly. The burgeoning energy consumption by hyperscale data centers emerges as an ur... » read more

New Memory Architecture For Local Differential Privacy in Hardware


A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

MIPI Deployment In Ultra-Low-Power Streaming Sensors


Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption if not conceived and executed carefully. A device like a high-resolution, high-frame-rate home security camera in a non-wired application requiring frequent battery changes or recharging will likely... » read more

Maximizing Energy Efficiency For Automotive Chips


Silicon chips are central to today’s sophisticated advanced driver assistance systems, smart safety features, and immersive infotainment systems. Industry sources estimate that now there are over 1,000 integrated circuits (ICs), or chips, in an average ICE car, and twice as many in an average EV. Such a large amount of electronics translates into kilowatts of power being consumed – equiva... » read more

The Future Of Memory


Experts at the Table: Semiconductor Engineering sat down to talk about the impact of off-chip memory on power and heat, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

IoT Building Block: Touch Interface HMI


Many IoT devices have started to include touch screen interfaces as part of their UI to make the devices more intuitive and easier to use. A great interface can make customers really love and want to use your IoT product, but a poor HMI interface makes the device unusable damaging the brand value. Given this impact a touch interface can have on your IoT device, it made me wonder what are the... » read more

RTL Optimization Best Practices Help To Achieve Power Goals And Identify Reliability Issues Earlier


Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality and higher performance in SoCs is rapidly stretching power budgets to their breaking point. Power must be considered at every stage of chip design. Waiting to address power until late in the design cycle – post-netlist or durin... » read more

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