ASIC/IC Trends With A Focus On Factors Of Silicon Success


“The more you know, the more you know you don't know.” ― Aristotle, 4th C. BC When Aristotle uttered this humble aphorism, he wasn’t telling us to throw up our hands and not bother with learning. He was encouraging us to continue digging deeper, to get answers and ask questions of those answers — that the thrills and rewards of study are truly without end. This is a big part of ou... » read more

Week In Review: Design, Low Power


Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

Target: 50% Reduction In Memory Power


Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Week In Review: Design, Low Power


Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs. TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logi... » read more

Week In Review: Design, Low Power


Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

Week in Review: Design, Low Power


The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

EDA Grabs Bigger Slice Of Chip Market


EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Efficient Hierarchical Verification For Low Power Designs


By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation


By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

Impacts Of Reliability On Power And Performance


Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

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