Leaning Into The SoC Power Methodology


As inflation skyrockets and the price of everything increases seemingly by the hour, finding ways to trim time and costs are more valuable than ever. Lean manufacturing was introduced by the Toyota Motor Corporation almost 100 years ago, laying the framework for future generations of manufacturing and industrial settings. Lean manufacturing is a methodology that focuses on minimizing waste w... » read more

Emulation-Centric Power Analysis Of SoC Designs


Verification expert Lauro Rizzatti recently interviewed Jean-Marie Brunet, senior marketing director, Scalable Verification Solutions Division (SVSD), Siemens EDA, about the importance of accurate power estimation and optimization for system-on-chip (SoC) designs. What is the problem facing the semiconductor industry today regarding pre-silicon power estimation? The problem is the discrep... » read more

Research Bits: April 19


Processor power prediction Researchers from Duke University, Arm Research, and Texas A&M University developed an AI method for predicting the power consumption of a processor, returning results more than a trillion times per second while consuming very little power itself. “This is an intensively studied problem that has traditionally relied on extra circuitry to address,” said Zhiy... » read more

Preparing For 3D-ICs


Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Early, Accurate, Signoff-Correlated Power Analysis


Power estimation has always been a fundamental part of semiconductor development, but it has grown in importance in recent years. Virtually every application domain has power limitations that must be satisfied before a chip is fabricated. There is no effective way to fix power issues in the lab or in the field, so pre-silicon estimation must be accurate. The short development cycles for many ty... » read more

Know Your Own Power, Early And Accurately


By Taruna Reddy and Vin Liao Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated p... » read more

Power Management Becomes Top Issue Everywhere


Power management is becoming a bigger challenge across a wide variety of applications, from consumer products such as televisions and set-top-boxes to large data centers, where the cost of cooling server racks to offset the impact of thermal dissipation can be enormous. Several years ago, low-power design was largely relegated to mobile devices that were dependent on a battery. Since then, i... » read more

Power Challenges In ML Processors


The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Speedcore Power Estimator User Guide


The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design. Read the Speedcore Power Estimator User Guide (UG073) here. » read more

Power Reduction In A Constrained World


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

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