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Author's Latest Posts


A Winning Formula


It may be fitting that DVCon will be held the same week as Super Tuesday this year, the day when the greatest number of states in the U.S. hold primary elections. Big dollar expenditures and return on investment (ROI) strategies are part of today’s political landscape, as they are with chip design and verification. Missing a delivery window for an electronics device can cost 25% or more o... » read more

How To Speed Up Networking Design Verification


The enormous growth of the Internet of things (IoT) has an enormous impact on network providers. After all, without the underlying network infrastructure, there would be no IoT. One consequence has been a significant increase in the number of Ethernet ports on networking devices. Today, Ethernet switches and routers reach 256 ports (by year’s end that number will increase to 1024 ports), a... » read more

The Old Two-Step Just Doesn’t Have That Swing


Power analysis has quickly become equally as important as functional verification for today's power-hungry SoCs. Yet, until now, it was not possible to fully analyze dynamic power in very large SoCs running embedded software. That day has finally arrived with new emulation platform software that overcomes the intrinsic shortcomings of the current two-step power estimation tools. The current ... » read more

The Power Estimation Challenge


If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely power the top Android devices released in 2015. The story broke in early December along the lines that the 810 had problems with overheating. Whet... » read more