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Leaning Into The SoC Power Methodology

Making the power analysis flow more efficient by performing experiments early.

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As inflation skyrockets and the price of everything increases seemingly by the hour, finding ways to trim time and costs are more valuable than ever. Lean manufacturing was introduced by the Toyota Motor Corporation almost 100 years ago, laying the framework for future generations of manufacturing and industrial settings.

Lean manufacturing is a methodology that focuses on minimizing waste within manufacturing systems while simultaneously maximizing productivity. The desired result of lean manufacturing is to reduce production times within the production systems and shorten response times from suppliers to customers.

Lean software development principles are as follows:

  • Desire to eliminate waste
  • Amplify learning
  • Decide as late as possible
  • Deliver as fast as possible
  • Empower the team
  • Build in quality
  • See the whole

For the purpose of this article, we will examine how the lean concept of eliminating waste can be applied to the SoC power analysis flow. By approaching power with a “lean lens,” we can look at ways to make the process more efficient while delivering the desired results.

Power: A fundamental challenge in the semiconductor industry

From battery-operated handhelds to datacenter servers, electronic devices are power consumers.  It was once said that semiconductors (chips) are heaters, and their byproduct is calculation.

Depending on the application area, total power consumption varies based on the semiconductor system-on-chip (SoC) content used, and the intended purpose for the device. One truth applies to every SoC – power analysis requires a holistic methodology, from architectural exploration to tape-out, to accurately address power concerns.

One of the key factors used to calculate the overall power consumption of a given device is to measure its dynamic power, which is the power consumed by the device when it is in full operation. Measuring dynamic power has become increasingly important when implementing SoCs in process technologies such as finFET. Here the gate area has increased; hence, the load capacitance is larger and the impact of the switching power more pronounced.

Time is of the essence

From the time of Francis Bacon (credited with first identifying the scientific process), the scientific and engineering community has worked constantly to develop ideas and put them through rigorous testing to ensure their validity and uncover possible trade-offs. When validating ideas becomes an extraordinarily lengthy process, it cripples the exploration of ideas and limits those involved to very basic trivial choices that could easily lead to accepting an answer rather than further exploring a desired range of possibilities.

Lean manufacturing is very keen on “rapid prototyping” or discovery experimentation techniques devised for learning and removing “conjecture” as much as possible out of the design process and  exploring vast scenarios quickly. The focus is really on an extremely short period of time to run many experiments, learn, and make decisions.

To address this, it is crucial to have a system that allows you to perform experimentations early (well in  advance of the RTL freeze stage) in the design cycle and provide a very fast turnaround time (multiple times per day rather than once or twice per month).

The Veloce Power App is a key technology from Siemens EDA that allows users to profile switching power for realistic software workloads (including OS and application software). This data, which could take days and weeks to produce for multi-processor SoCs, can be generated in a matter of hours with Veloce Power App technology.

In addition, by capturing data at every cycle, this technology enables detailed analysis that was completely out of scope for real benchmarks. Users get insight that can be shared with designers to modify their design to improve power consumption and validate it. More importantly, this is being done early in the design cycle with RTL or even earlier with virtual platforms, or models of the design’s functionality. There is a significant advantage when results of power analysis can be applied early. It makes it possible to react and readjust as the design description becomes more stable.

Lean enough?

The Veloce Power App has three primary paths to help engineers acquire power data:

  • Stimulus (vector) generation for power tools
  • Generating a power profile and heat map
  • Calculating an activity factor

Realistic stimulus/workloads play a huge role when estimating and analyzing the power consumption of an SoC. Using functional verification tests may only lead to overly pessimistic or overly optimistic estimates. This is our observation after working with more and more companies who run real workloads with firmware, OS and real applications to generate stimulus for power tools. Historically, this data (if possible) was generated in a VCD/FSDB format, and later fed to power tools, as shown in figure 1.

By applying the first principle of a lean philosophy and observing the data flow, astute developers of the Veloce Power App observed several opportunities for lean improvement to the flow, and when made reduced a significant amount of systematic waste. The result was an API-based flow that enables more effective use of the data.

A game-changer

Veloce PowerStream is the latest innovation to the Veloce Power App. Veloce PowerStream allows power profiling at hundreds of KHZ (at real emulation speed). It also enables complete power profiling of realistic workloads and benchmarks deemed impossible before. For instance, a complete power profile of the Car Chase benchmark (Kishonti) was captured on Veloce using Veloce PowerStream technology in less than an hour while running on a big multi-core GPU. Typical power tools require a minimum of multiple weeks of processing to get a portion of this data and that’s based on the uncertain possibility of it happening at all. The Veloce Power App with Veloce PowerStream technology is completely scalable, and its runtime does not degrade with bigger design size.

With Veloce PowerStream, there is a significant reduction in waiting, overprocessing, and data movement. In addition, the Veloce Power App monitors key power indicators (KPI) and metrics that significantly impact the power profile of a design, including:

  • Static data from design related register, memory, clock-gating, etc.
  • Register, clock, and combinational power
  • Clock gating indicators (CGE, FFE)
  • UPF power domain information

In addition, with Veloce PowerStream power profiles and heat maps of a full SoC can be generated within a couple of hours while running real applications for billions of cycles. The design team can explore micro-architectural choices while running real applications and measure the impact on both power and performance to find the balanced trade off.

The software team, meanwhile, can explore the interactions between firmware, power conscious scheduler, operation system, applications, and various settings and measure both power and performance on real applications.

To support the use of these KPIs and metrics, Veloce Power App provides a comprehensive KPI visualization dashboard connected to the Veloce data analytics database that allows a user to:

  • Make comparisons based on the analysis of all KPIs among different RTL/design versions
  • Drive deep dive analysis of power trends of multiple workloads

New innovations in the Veloce Power App promise to make your power analysis process as lean as possible without compromising time, accuracy, or the ability to reach the power goals you have for your design.



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