Author's Latest Posts


Chiplets – Taking SoC Design Where No Monolithic IC Has Gone Before


The chiplet movement is a reaction to the rapidly changing IC landscape and the current IC fabrication realities. Engineers are increasingly realizing that it makes little sense to integrate every IP block in a system on one piece of silicon if the fit is poor. There are many advantages with monolithic silicon integration, but those advantages are rapidly being outweighed by the economics of bu... » read more

Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs


New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore embedded FPGAs (eFPGAs), enabling users to regain a highly prof... » read more

Speedchip FPGA Chiplets


Next-generation SoC platforms are evolving rapidly to process and move enormous amounts of data from the edge; over the network and to the cloud for high data and compute intensive applications such as AI and machine learning, high-performance computing (HPC) and autonomous driving. As a result, next-generation ASICs need to be larger, faster and further optimized for performance, power and are... » read more

Speedcore Power Estimator User Guide


The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design. Read the Speedcore Power Estimator User Guide (UG073) here. » read more

Achieving ASIC Timing Closure With Speedcore eFPGAs


Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is ... » read more

The Ideal Solution For AI Applications — Speedcore eFPGAs


AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and s... » read more

2018 Ushers In A Renewed Push To The Edge


The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centra... » read more

eFPGA Acceleration in SoCs


The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedd... » read more

Evaluating Speedcore IP For Your ASIC


By exploiting Achronix Speedcore embedded FPGA (eFPGA) IP — IP proven in multiple ASIC designs for wireless, datacenter and high-performance computing (HPC) applications — designers of SoCs can now add logic programmability to their solution, resulting in a single ASIC that can adapt to many applications. While many system architects may already have strong ideas on how an eFPGA core could ... » read more

Embedded FPGA Acceleration In SoCs


The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedd... » read more

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