Eight Benefits Of Using An FPGA With An On-Chip High-Speed Network

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. A consequence of this limitation is that designers often spend much of their development time trying to achieve timing closure, sacrificing performance in order to place and route their design.

Traditional FPGA routing is based on many individual segments that run horizontally and vertically throughout the FPGA, with switch boxes at the intersections of the horizontal and vertical routes to enable paths to be connected. A path from any source to any destination on the FPGA can be made with these segments and switch boxes. This uniform structure of FPGA routing enables extreme flexibility in implementing any logic function, for any data path width within the FPGA fabric.

While the bit-wise routing in FPGAs is very flexible, it has the downside in that each segment adds delay to any given signal path. Signals that need to span long distances in the FPGA will incur the delays of each of the connecting segments, slowing the performance of the function. Another challenge with bit-wise routing is congestion, which requires signal paths to detour around the congestion, which can incur more delays and causes the performance to degrade further.

Achronix saw this challenge as an opportunity to develop a new architecture that could eliminate traditional FPGA design challenges and increase system performance. Achronix’s solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family. The Speedster7t NoC connects to all of the on-chip high-speed interfaces: multiple ports of 400G Ethernet, PCIe Gen5, GDDR6 and DDR4/5.

The interior of the NoC consists of an array of rows and columns that distribute network traffic horizontally and vertically throughout the FPGA fabric. Master and slave NoC access points (NAPs) at the location where each row and column of the NoC cross. These NAPs can be a source or destination between the NoC and the programmable fabric.

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