Deriving Configuration Time For eFPGAs


Part 1 of this blog post described how to configure an eFPGA, using Achronix’s Speedcore eFPGA as an example. It explained why each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up due to its nonvolatile SRAM technology to store configuration bits. This post will detail how the configuration time is derived, once again using Speedcore eFPGA as th... » read more

Achieving ASIC Timing Closure With Speedcore eFPGAs


Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is ... » read more

Partitioning Drives Architectural Considerations


There are multiple reasons for design partitioning. One is complexity, because it’s faster and simpler to divide and conquer, particularly with third-party IP. A second reason involves power, where it may be more efficient to divide up functionality so each function be right-sized. A third involves performance, where memory utilization and processing can be split up according to functional pr... » read more

The Rising Cost Of 5G


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Week in Review: IoT, Security, Auto


Cybersecurity Check Point Software Technologies reports that facsimile machines (yes, people still use them!) can be subject to hacking through vulnerabilities in their communication protocols. The HP Officejet Pro All-in-One fax printers and other fax machines can be compromised with a hacker only knowing a fax number, according to the company. Check Point Research says a design flaw in Andro... » read more

Week in Review: IoT, Security, Auto


Cybersecurity Jens (Atom) Steube, a cybersecurity researcher and creator of the Hashcat password cracking tool, was probing for vulnerabilities in the new WPA3 security standard for Wi-Fi routers. WPA3 presents a robust defense against hacking, yet Steube discovered a security flaw in routers using WPA/WPA2 – one that leaves Wi-Fi passwords enabled with Pairwise Master Key Identifiers vulner... » read more

Week In Review: Design, Low Power


Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Embedded FPGA Timing


Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

The Importance Of An eFPGA’s Configuration Interfaces


eFPGAs are heralded throughout the semiconductor industry for their flexibility and programmability, especially when it comes to high-performance compute applications. Let’s take a closer look at how an eFPGA is configured. Each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up because this eFPGA employs nonvolatile SRAM technology to store its co... » read more

New 5G Hurdles


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

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