Week In Review: Design, Low Power

NSTC to boost chiplet standards; reconfigurable DSP and AI inference IP; making semiconductor qubits; 112G SerDes IP; TSMC certifications.


The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, including fabless companies.

The NSTC, which will be operated by a public-private consortium, will provide companies, academic institutions, and research organizations throughout the semiconductor ecosystem access to emerging materials and process technologies, IP and design tools, reference flows and process design kits, a chiplet stockpile, access to physical assets such as end-to-end prototyping and multi-project wafer schemes, and incubation support for startups. It will also focus on workforce development, including providing academic institutes with access to state-of-the-art design environments and infrastructure, process design kits, and circuit design libraries.

NIST expects to work with the NSTC and industry standards bodies to develop standards in emerging areas including chiplets, advanced packaging, and heterogeneous integration. The document also points to a role it hopes NSTC will play in collecting and aggregating data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models, and creating a methodology to share those data sets that protects proprietary component information while enabling access to appropriate performance data.

Separately, NIST will establish the National Advanced Packaging Manufacturing Program (NAPMP) to drive research and development of advanced packaging technologies, materials, substrate fabrication, tools, design, and test. NSTC and NAPMP are also expected to work with the proposed CHIPS Metrology Research Program, the Manufacturing USA institutes, and the military-focused DOD Microelectronics Commons.

NIST is currently soliciting nominations for a committee that will select the board of trustees for NSTC.

Argonne National Laboratory opened the Argonne Quantum Foundry to develop, test, and fabricate semiconductor qubits. It will also provide a U.S. supply chain of materials for both foundational science and industry research. The foundry also features a prototype silicon-based quantum computer. The data collected at the foundry will be used to build a national database of materials and their properties. A second foundry, focused on superconducting materials for quantum computing, will open soon at the SLAC National Accelerator Laboratory.

Thermal integrity is becoming much harder to predict accurately in 2.5D and 3D-IC, creating a cascade of issues that can affect everything from how a system behaves to reliability in the field. And while a number of tools exist to understand and model thermal effects in heterogenous silicon interposer designs, it isn’t always clear exactly what the tools are supposed to do and how all the pieces fit together.

Gartner forecasts that semiconductor revenue will decline 11.2% in 2023, reaching $532 billion. However, it sees an upswing in 2024 of 18.5%. The memory market is even more dramatic: the firm projects a decline of 35.5% in 2023 but believes it is on pace to rebound in 2024 with a 70% increase. Gartner also notes that while the PC, tablet and smartphone semiconductor markets are stagnating, while the automotive and industrial, military/civil aerospace semiconductor markets will achieve growth, with automotive forecast to grow 13.8%, reaching $76.9 billion in 2023.

TrendForce reported that the ton ten IC design houses saw a 9.2% quarter-over-quarter decline in revenue in Q4 2022. It expects the decline to continue into Q1 2023. Meanwhile, design IP revenues were up 20.2% in 2022, reaching $6.7 billion, according to IPnest.

Tools, IP, products

Flex Logix unveiled new IP and software for DSP and AI inference based on the reconfigurable InferX hardware. The DSP combines InferX with Softlogic for DSP operations such as FFT that is on-the-fly switchable between sizes, FIR filters of any number of taps, and Complex Matrix Inversions of any size. The AI offering is InferX hardware combined with a compiler that takes in a customer’s neural network model in Pytorch, Onnx or TFLite formats, quantizes the model with high accuracy, compiles the graph for high utilization, and generates the run time code that executes on the hardware.

Cadence unveiled 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, AI/ML accelerators, switch fabric SoCs, and 5G wireless infrastructure. The ELR SerDes PHY supports insertion loss of 43db with BER of 10e-7 and enables system robustness for lossy and reflective channels observed in open box platforms as well as lengthy direct attach copper cables. The company also announced that its 112G-LR SerDes was silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC).

In recent weeks, the three largest EDA vendors have made sweeping announcements about incorporating machine learning into their tools at their respective user events, and the entire chip industry is heading in a similar direction. Machine learning, which teaches a machine how to perform a specific task based upon pattern recognition, is a natural fit for chip design. Reinforcement learning, which rewards behavior on a sliding scale and dynamically adjusts, is the primary method being deployed today.

Infineon Technologies debuted a 1200 V half-bridge driver IC family with active Miller clamp for optimized ruggedness. The devices offer negative VS transient immunity, shoot-through protection, undervoltage lockout and fast overcurrent protection. It targets high power applications such as commercial HVAC systems, heat pumps, servo drives, industrial inverters, pumps, and fans up to 10 kW.

Renesas Electronics introduced an NB-IoT chipset specifically for the Indian market. It particularly targets smart power and water meter applications.

Agile Analog launched a range of digitally wrapped analog IP subsystems covering power management, PVT sensing, and sleep management. The subsystems can be dropped into a digital design flow and connected via a standard peripheral bus, such as AMBA APB. They are customizable and process and foundry agnostic.

Rapid Silicon uncorked eFPGA IP with a customizable and scalable architecture that allows the design of custom eFPGA from 1.5K to 100K+ logic cells with configurable BRAM and DSP MAC tiles.

Semidynamics announced a family of customizable 64-bit RISC-V IP cores optimized for handling large amounts of data in applications such as AI/ML and HPC.

Esperanto Technologies says it has ported and is running a range of Generative AI models on its low power RISC-V hardware. It plans to make access available to the RISC-V research community.

POET Technologies introduced a packaged light source solution for photonic AI applications. It integrates active components like lasers and certain other passive optical and electrical components into the optical interposer to provide a complete light source solution that can be integrated on a host board and connected to chips and ASICs with built-in silicon photonics.


Axelera AI licensed Arteris IP’s FlexWay network-on-chip system IP. It will be used for SoC connectivity in the Metis AI hardware and software platform for computer vision AI inference at the edge. The FlexWay IP uses area-optimized interconnect components to address a smaller class of SoC and is compatible with Arm AMBA AXI and AHB standards.

Fraunhofer IIS EAS and Achronix are teaming up to build a multi-chip system composed of several chiplets and to validate performance and interoperability of chip-to-chip transaction layer interconnects such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe). The project will create a demonstration platform suitable for applications such as 5G/6G wireless infrastructure, ADAS, and high-performance test and measurement equipment. One key application that will be covered is the connection of high-speed ADCs together with eFPGA IP for preprocessing in radars as well as wireless and optical communication.

Alps Alpine selected Siemens’ Symphony platform for mixed-signal applications when developing and verifying its newest functionally safe capacitance detection IC. The IC enables proximity, touch, and spatial gesture detection across a range of human-machine interface systems in applications such as automotive and smart devices.

Infineon and Schweizer Electronic are teaming up to embed Infineon’s 1200 V CoolSiC chips directly onto PCBs to improve performance and reduce costs for electric vehicles. Embedding a 48 V MOSFET in the PCB resulted in a 35% increase in performance.

A 6G testbed operated as a collaboration between Keysight Technologies, the National Physical Laboratory (NPL), and the University of Surrey made the first 6G connection at speeds greater than 100 Gbps over sub-terahertz (THz) frequencies in the U.K. The demonstration was made at a frequency of 300 GHz using both 32 and 64 quadrature amplitude modulation (QAM).

STABL Energy is using MOSFETs from Infineon to make stationary energy storage systems from retired electric passenger car batteries. The system can connect discarded batteries with different residual capacities to the public power grid, even in larger quantities, without a central inverter.

TSMC certifications, collaborations

TSMC announced its N2 process, which leverages nanosheet transistors to offer up to 15% speed improvement at the same power or 30% power reduction at the same speed when compared with the TSMC N3E process, with a 1.15X increase in chip density. More details on the foundry’s numerous other technology announcements can be found in the Semiconductor Manufacturing and Test week in review.

Gate-all-around FETs like nanosheets will have a significant impact on how chips are designed, but the industry still does not know much about these devices, or how significant some of the issues, like variability, will be long-term.

Ansys’ Redhawk-SC and Totem power integrity platforms were certified for power integrity signoff in TSMC’s N2, including the effects of self-heat on long-term reliability of wires and transistors using a heatsink-aware flow that increases thermal predictive accuracy by taking into consideration the heat conduction to neighboring wires that may cool a local hot spot.

Cadence revealed a node-to-node design migration flow compatible with all TSMC advanced nodes, including N3E and N2. The Virtuoso Design Platform automatically migrates schematic cells, parameters, pins, and wiring from one TSMC process node to another. The Virtuoso ADE Product Suite’s simulation and circuit optimization environment then tunes and optimizes the new schematic to ensure the design achieves all required specifications and measurements. Additionally, the company’s digital and custom/analog flows were certified for TSMC’s N3E and N2 nodes, with PDKs available. Design flows using the Integrity 3D-IC platform were optimized to support the TSMC’s 3Dblox for 3D front-end design partitioning in complex systems. Cadence also taped out its 16G UCIe 2.5D advanced package IP on TSMC’s N3E process technology using the 3DFabric CoWoS-S silicon interposer technology for heterogeneous integration of UCIe PHY and controller.

Several Siemens tools were certified for TSMC processes, including Calibre nmPlatform tool for IC verification sign-off for TSMC’s advanced N3E and N2 processes; mPower analog software for transistor-level electromigration and IR drop sign-off for the N3E process; Tanner software for analog and mixed-signal ICs for 16nm; and Analog FastSPICE platform for circuit verification of nanometer analog, RF, mixed-signal, memory, and custom digital circuits for N5A, N3E, and N2 processes. Analog FastSPICE also adds support for TSMC’s Reliability Aware Simulation technology to address IC aging, real-time self-heating effects, and other reliability features.

Synopsys is working with TSMC on digital and custom design EDA flows for TSMC’s N2 process. Synopsys is also providing an analog migration flow for migration of N4 and N5 designs to N3E. Additionally, Synopsys implementation and signoff solutions are integrated with Ansys multi-physics analysis technology for design and power and thermal signoff critical of multi-die systems using TSMC’s 3DFabric technologies and 3Dblox standard. Synopsys’ UCIe PHY IP was also taped out on the TSMC N3E process to enable multi-die systems.

Synopsys, Ansys, and Keysight Technologies announced a new 79GHz mmWave RF design reference flow for the TSMC 16nm FinFET Compact Technology (16FFC). The reference flow enables the implementation of reliable, 79-GHz transceiver ICs for advanced autonomous systems that require independent operation without human intervention such as automotive radar, 5G connectivity, security applications, and environmental monitors.

Cadence also optimized its Virtuoso platform for the 79GHz mmWave design reference flow on TSMC’s N16 process.

Research notes

A device developed by Princeton University researchers could help extend the range of 5G mmWave signals. Called ‘mmWall,’ the tablet-sized device can steer mmWave signals to reach all corners of a large room, and, when installed in a window, can bring signals from an outdoor transmitter indoors. The mmWall is an accordion-like array of 76 vertical panels that can both reflect and refract radio waves at frequencies above 24 gigahertz, the lower bound of mmWave signals. Each panel of mmWall holds two meandering lines of thin copper wire, flanking a line of 28 broken circles made of thicker wire, creating ‘meta-atoms’ with tunable electrical and magnetic properties. Applying controlled electrical current to these meta-atoms can change the behavior of the mmWave signals that interact with the mmWall surface, dynamically steering the signals around obstacles by shifting their paths by up to 135 degrees.

Researchers at Linköping University and the KTH Royal Institute of Technology developed a transistor made of wood. The researchers used balsa wood to create their transistor, as the technology involved requires a grainless wood that is evenly structured throughout.  They removed the lignin, leaving only long cellulose fibers with channels where the lignin had been. These channels were then filled with a conductive plastic, or polymer, called PEDOT:PSS, resulting in an electrically conductive wood material. This was used to build the wood transistor, which was able to regulate electric current and provide continuous function at a selected output level. It could also switch the power on and off, although with a delay of about a second to switch off, and five to switch on. “Yes, the wood transistor is slow and bulky, but it does work, and has huge development potential,” said Isak Engquist, senior associate professor at the Laboratory for Organic Electronics at Linköping University.

Screens and other devices relying on transparent conductors can be made without the rare earth element indium, report Purdue University researchers. The new transparent organic conductors use polymers using carbon-based materials that have a lower manufacturing cost and are easier to manufacture into thin films than indium through solution-coating processing. Performance of the new thin-film transparent conductors also rivals that of conductors made with indium tin oxide, according to Jianguo Mei, associate professor of chemistry at Purdue. “The polymer ink is shelf-stable for months under ambient conditions, compared to commercially available PEDOT:PSS. Our new transparent organic conductors exhibit low sheet resistance and high transmittance compared to any other solution processable transparent conductors. Also, it exhibits excellent durability under accelerated weathering tests.”

Upcoming events

  • IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – May 1-4 (San Jose, CA)
  • Women in Semiconductor: WIS 2023 – May 1 (Saratoga Springs, NY)
  • ITF World 2023 – May 16-17 (Antwerp, Belgium)
  • Annual ESD Alliance Membership Meeting & CEO Outlook – May 18 (Santa Clara, CA)
  • International Memory Workshop – May 21-24 (Monterey, CA)
  • Embedded Vision Summit – May 22-24 (Santa Clara, CA)
  • RISC-V Summit Europe – June 5-9 (Barcelona, Spain)
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • Thermal Integrity Challenges Grow In 2.5D
  • What Designers Need To Know About GAA
  • Transitioning To Photonics
  • EDA Makes A Frenzied Push Into Machine Learning
  • True 3D-IC Problems
  • Designing For In-Circuit Monitors
  • RISC-V Driving New Verification Concepts

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