Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

Chip Industry’s Technical Paper Roundup: Jan. 8


New technical papers added to Semiconductor Engineering’s library this week. [table id=183 /] More ReadingTechnical Paper Library home » read more

Design Space Simulator Of Distributed Multi-Chiplet Manycore Architectures For Comm-Intensive Applications


A technical paper titled “Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems” was published by researchers at Princeton University. Abstract: "Current design-space exploration tools cannot accurately evaluate communication-intensive applications whose execution is data-dependent (e.g., graph analytics and sparse linear algebra) on scale-out manycore sys... » read more

Chip Industry’s Technical Paper Roundup: Dec 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=171 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Chiplet Architecture: Scalable and Cost-Efficient Systems for Irregular Applications (Princeton)


A new technical paper titled "DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications" was published by researchers at Princeton University. Abstract "In recent years, the growing demand to process large graphs and sparse datasets has led to increased research efforts to develop hardware- and software-based architectural solutions to accelerate them. While... » read more

DRAM Choices Are Suddenly Much More Complicated


Chipmakers are beginning to incorporate multiple types and flavors of DRAM in the same advanced package, setting the stage for increasingly distributed memory but significantly more complex designs. Despite years of predictions that DRAM would be replaced by other types of memory, it remains an essential component in nearly all computing. Rather than fading away, its footprint is increasing,... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)


A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Chip Industry’s Technical Paper Roundup: Sept 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=141 /] More Reading Technical Paper Library home » read more

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