Enabling 2.5D/3D Multi-Die Package


In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technolo... » read more

Week In Review: Semiconductor Manufacturing, Test


China retaliated against a U.S. embargo on advanced semiconductor equipment exports by restricting exports of gallium and germanium. Both metals are widely used in semiconductors and electric vehicles. Despite export controls for advanced chips and equipment imposed on Chinese foundries by the U.S. and its allies, TrendForce predicts China's 300mm market share likely will increase from 24% ... » read more

Week In Review: Design, Low Power


The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, ... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Renesas introduced a narrowband Internet of Things (NB-IoT) chipset and dev kit for the Indian market. The LTE NB-IoT modem chipset, the RH1NS200, was designed for Indian telecommunications carriers by targeting bands 1,3, 5 and 8 and by following India’s carrier-approved LTE protocol stack and software suite. Low power usage is built in — it has a low Power Saving Mode... » read more

Week In Review: Design, Low Power


Worldwide semiconductor revenue increased 1.1% in 2022 to $601.7 billion, up from $595 billion in 2021, according to preliminary results from Gartner. The combined revenue of the top 25 semiconductor vendors increased 2.8% in 2022 and accounted for 77.5% of the market. The memory segment posted a 10% revenue decrease. Analog showed the strongest growth, up 19% from 2021, followed by discretes, ... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Keysight Technologies introduced its new Electrical Performance Scan (EP-Scan), a high-speed digital simulation tool for rapid signal integrity (SI) analysis for hardware engineers and printed circuit board (PCB) designers. Siemens Digital Industries Software announced the opening of its eXplore Live at The Smart Factory @ Wichita, housed at Wichita State University’... » read more

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization


Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

Week In Review: Design, Low Power


Synaptics will acquire DSP Group, a provider of voice and wireless chipset solutions for converged communications, at $22.00 per share in an all-cash transaction. The deal is worth $538 million. "We continue to invest in technologies that tilt our product mix toward IoT applications," said Michael Hurlston, President and CEO of Synaptics. "DSP Group's expertise in SmartVoice and ULE wireless so... » read more

Challenges In Developing A New Inferencing Chip


Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, sat down with Semiconductor Engineering to explain the process of bringing an inferencing accelerator chip to market, from bring-up, programming and partitioning to tradeoffs involving speed and customization.   SE: Edge inferencing chips are just starting to come to market. What challenges di... » read more

Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

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