Week In Review: Design, Low Power

Cadence buys data center twin company; earlier physical verification; virtual peripherals for RISC-V; mixed-signal UVM; hybrid quantum-classical programming.


Tools & IP

Cadence will acquire Future Facilities, a provider of electronics cooling analysis and energy performance optimization solutions for data center design and operations using physics-based 3D digital twins. Future Facilities’ product portfolio includes an electronics thermal solution, as well as computational fluid dynamics (CFD) electronics cooling simulation technology that optimizes the performance and cooling efficiency of data centers. Their technology creates a 3D digital twin that allows operators to predict, visualize, and quantify the impact of any change in the data center prior to implementation and during operations. “Using advanced CFD brings tremendous benefits when analyzing thermal efficiencies in the data center,” said Hassan Moezzi, founder and CEO of Future Facilities. “We are excited to join the Cadence team and look forward to combining our data center and electronics technology solutions with Cadence’s expertise in Intelligent System Design to further advance performance, sustainability and energy efficiency from chip design to all elements of the data center right up to the chillers that are critical components in data center design and operations.” Terms of the deal were not disclosed.

Siemens Digital Industries Software expanded its physical verification platform to add physical verification capabilities earlier in the design flow. Among the additions is in-design, signoff-quality Calibre DRC for custom, analog/mixed-signal, and digital designs; automated analysis of immature and incomplete designs across blocks, macros, and full-chip layouts to find and fix high-impact physical layout earlier in the design and verification flow; and automated analysis of immature and incomplete designs for circuit verification use models.

Imperas extended the RISC-V Verification Interface (RVVI) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts. The addition allows the reuse of components from the Open Virtual Platforms library of open-source models. RVVI is an open specification that provides a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation. “All the significant progress in processor innovation can be traced back to two fundamental building blocks: Abstractions and Standards,” said Simon Davidmann, CEO at Imperas Software.  “Simulation of the latest designs with billions of transistors is achieved through abstraction, similarly the success of IP reuse has been enabled by standards. Now the emerging RISC V verification ecosystem can build on the open standard RVVI flexible framework as a basis for verification IP and quality testing methods.”

Siemens also introduced the Symphony Pro platform that extends Universal Verification Methodology (UVM) and Unified Power Format (UPF) driven low-power techniques into the mixed signal domain with fast simulation in a unified environment. STMicroelectronics and Silicon Labs noted using the tool. “Mixed-Signal functional verification is increasingly vital for our sophisticated designs targeted for the imaging and automotive industries. We’ve participated in the early access program for Symphony Pro and have seen significant productivity gains thanks to advanced debugging capabilities and seamless support for multi-layer sandwich configurations in Symphony Pro,” said Stephane Vivien, senior CAD manager, Imaging Division, STMicroelectronics.

Synopsys developed an RF design reference flow and companion design solutions kit (DSK) for Samsung Foundry’s 8nm RF low-power FinFET process. The reference flow documents a methodology for RF design with Synopsys and Ansys tools that spans schematic design, simulation, layout, extraction, electromagnetic (EM) simulation, and physical verification. The associated DSK includes a set of application notes, tutorials, and design examples that cover advanced design methodology topics.

Flex Logix joined an effort led by Microsoft to develop a chip development platform with a focus on security. “Security can mean a lot of different things. For eFPGA, it means providing a means for keeping circuitry secret by programming the eFPGA in a secure environment,” said Geoff Tate, CEO and Co-founder of Flex Logix. Part of the U.S. Department of Defense’s Rapid Assured Microelectronics Prototypes (RAMP) program, the Advanced Commercial Capabilities project will utilize eFPGA to provide the capability to make silicon changes to update algorithms or modify functionality in long-lifetime DoD systems. “Our collaboration with Flex Logix will help to advance flexibility to chip design,” said Mujtaba Hamid, General Manager, Silicon, Modeling and Simulation, Microsoft. “The company’s eFPGA technology has demonstrated success in supporting mission-critical applications and we look forward to bringing this capability to support national security priorities.”

Cadence and Tower Semiconductor are developing an automotive reference design flow using the Cadence Virtuoso Design Platform and Spectre Simulation Platform to provide a unified design environment for chip and package co-design and simulation.

Inuitive deployed Arteris IP’s FlexNoC interconnect IP for its next generation of computer vision platforms based on Inuitive’s Vision-on-Chip processors. “Arteris IP interconnects enable us to meet our performance goals and facilitate the scalability of future products, helping us to accelerate our innovations,” said Dor Zepeniuk, CTO and VP product at Inuitive.

Qualcomm used Keysight’s virtual instrument systems architecture (VISA) library software in combination with the Qualcomm Development Acceleration Resource Toolkit automation tool to achieve an interoperability development test milestone for Arm-based 5G PCs powered by Windows on Snapdragon Compute Platforms. The VISA software provides communication between the device under test and the test instrument across any input/output software layer.

Achronix adopted Ansys’ multiphysics simulation solutions to verify thermal reliability and power integrity of IP blocks and analyze electrostatic discharge (ESD) circuits in its latest FPGA. “Advancing to 7nm silicon process technology improves our device performance but also increases our need for multiphysics verification,” said Chris Pelosi, vice president of hardware engineering at Achronix.

Codasip and Breker Verification Systems will collaborate to develop and improve verification processes for common RISC-V SoC scenarios such as cache coherency, security, and power management, resulting in a prescribed flow for RISC-V SoC verification.

EdgeCortix developed a new compiler for Renesas’ DRP-AI accelerator. The new compiler is available with associated software and tools and works in combination with Renesas’ DRP-AI tools. It expands model support and adds support for floating-point 16 bit, as well as adding PyTorch and improved ONNX support, with TensorFlow to follow.

AI-LINK selected Keysight’s 5G test tools for end-to-end performance validation of cloud-native 5G radio access network (RAN) equipment in a digital twin laboratory environment. The user equipment emulation solution UeSIM and LoadCore, a cloud-native 5G core (5GC) network test solution, were used to simulate a large number of industrial mobile devices designed for deployment in 5G private networks.

EDA industry revenue increased 12.1% from $3,157.7 million in Q1 2021 to $3,540.5 million in Q1 2022, according to the ESD Alliance. “Product categories Computer-Aided Engineering, Printed Circuit Board and Multi-Chip Module, Semiconductor Intellectual Property, and Services recorded growth for the quarter,” said Walden C. Rhines, Executive Sponsor of the SEMI Electronic Design Market Data report. IP revenue had the biggest increase, jumping 23.7% to $1,376.5 million, with the four-quarter moving average up 26.5%. Services weren’t far behind, with a revenue increase of 22.7% to $121.4 million and a four-quarter moving average increase of 24.9%.

Quantum & data center

Nvidia unveiled its Quantum Optimized Device Architecture (QODA), an open, unified environment that aims to make quantum computing more accessible by creating a coherent hybrid quantum-classical programming model. It enables developers to build complete quantum applications simulated with the company’s cuQuantum SDK on GPU-accelerated supercomputers. “The hybrid quantum-classical capabilities developed by Nvidia will enable HPC developers to accelerate their existing applications by providing an efficient way to program quantum and classical resources in a consolidated environment,” said Yudong Cao, chief technology officer at Zapata. Nvidia also announced QODA collaborations with quantum hardware providers IQM Quantum Computers, Pasqal, Quantinuum, Quantum Brilliance, and Xanadu; software providers QC Ware and Zapata Computing; and supercomputing centers Forschungszentrum Jülich, Lawrence Berkeley National Laboratory, and Oak Ridge National Laboratory.

Quantinuum and JSR Corporation will work together on a project using quantum computers to model semiconducting materials, such as metal complexes and transition metal oxides. They will develop quantum algorithms and methods based on dynamical mean-field theory, which could provide a more accurate understanding of the electronic properties of complex organic and inorganic materials, such as optical absorption and conductivity.

Google Cloud announced its first VM family based on the Arm architecture, Tau T2A, which use the Ampere Altra CPU, based on the Arm Neoverse N1 core. The Tau family of VMs is optimized for cost-effective performance for scale-out workloads. Tau T2A VMs come in multiple predefined VM shapes, with up to 48 vCPUs per VM, and 4GB of memory per vCPU. They offer up to 32 Gbps networking bandwidth and a range of network attached storage options.


Nordic Semiconductor will acquire Mobile Semiconductor, a provider of highly optimized embedded SRAM for MCUs and SoCs. Its products have been included in Nordic Semiconductor’s own nRF52 and nRF53 Series SoC and nRF91 Series System-in-Package (SiP) devices. “As IoT applications continue to become ever more capable and high performance, memory has become an increasingly vital ingredient of the ultra-low power mix. Nordic has relied on Mobile Semiconductor’s embedded SRAM technology for many years to achieve this. Bringing that expertise in-house will position us extremely well when it comes to developing highly optimized future products,” said Kjetil Holstad, Nordic’s EVP of Product Management. Cameron Fisher, CEO at Mobile Semiconductor, added, “As the technology becomes more advanced, customers benefit from the resources larger companies have to continuously invest in R&D. We believe Mobile Semiconductor has grown as far as it can as a private company and now needs a company like Nordic Semiconductor to take our memory architectures to the next level. Nordic Semiconductor’s leadership in providing low power and low leakage devices is the perfect match for Mobile Semiconductor and this acquisition extends our technology’s reach.” Terms of the deal, which is expected to close in Q3 2022, were not disclosed.

Samsung Electronics started sampling 16Gb DDR6 DRAM featuring 24Gbps processing speeds. Built on Samsung’s third-generation 10-nanometer-class (1z) process using EUV technology, the new memory is targets next-generation graphics cards, laptops, and game consoles, as well as AI-based applications and HPC systems. It utilizes dynamic voltage switching (DVS) to adjust the operating voltage depending on performance requirements, which the company says will provide approximately 20% higher power efficiency at 1.1V, compared to the 1.35V GDDR6 industry standard.

Power devices

Gallium nitride power IC company Navitas Semiconductor acquired VDD Tech, a provider of advanced digital-isolators for next-generation power conversion. The company says its dV/dt sensing, blanking, and refresh technologies enable an very-high-voltage-isolation capability with high frequency of operation. “VDD Tech’s isolation technology is a key part of our growing power-and-control integration strategy, creating an additional $1B/yr market opportunity,” said Gene Sheridan, Navitas CEO and co-founder.

Infineon introduced new point of load DC-DC buck regulator power modules with an integrated inductor that offer high-efficiency continuous 3A/4A load capability and line regulation over a 4.5 – 14 V input supply range. The modules have a 10 μA supply current at shutdown for longer battery life in portable applications.

Read more

Find more of the week’s news at Manufacturing, Test and Auto, Security, Pervasive Computing.

The burden for ensuring IC reliability is shifting left, in the latest Systems & Design newsletter. Other stories highlight why getting hardware-dependent software right is critical and how the talent crunch is driving EDA to embrace big data.

Find out if analog can make a comeback in the latest Low Power-High Performance newsletter. Plus, read why thermal issues in DRAM are reaching a crisis point and whether the IP industry is ready to undergo a transformation.

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