Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Shift-left Schematic Memory Contention Analysis

By Siemens EDA - 11 Jun, 2026 - Comments: 0

Insight Analyzer streamlines memory block design by enabling early detection of memory contention at the schematic level. This shift-left approach lets design teams optimize architectures, mitigate risks and address reliability concerns before layout and manufacturing, helping to avoid costly rework and delays. Designers gain actionable analysis and clarity for complex memory block structures, ... » read more

From Billions Of Violations To Actionable Insights: Calibre Vision AI

By Siemens EDA - 29 May, 2026 - Comments: 0

As advanced node SoCs increase in size and complexity, early full-chip DRC runs frequently produce hundreds of millions to billions of violations. This overwhelming scale leads to new challenges—not just in running checks, but in comprehending results, setting priorities, and coordinating closure across teams. Introduced in 2025, Calibre Vision AI enabled instance-complete, AI-guided triage a... » read more

Enabling A Critical Phase in SoC Development

By Siemens EDA - 06 May, 2026 - Comments: 0

High speed execution of an SoC model on an FPGA-based prototyping system is essential—both to permit development and verification of the full software stack and to understand hardware/software interactions—before silicon is available. But for SoC designs that include high-speed, voluminous I/O, it is equally essential that the prototype be exercised with large amounts of real-world I/O o... » read more

Extraction Challenges of CFET and Backside Power Delivery

By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

System-level Reliability Verification for 2.5D/3D ICs Using Innovator3D IC and Calibre 3DPERC

By Siemens EDA - 04 Mar, 2026 - Comments: 0

The increasing demand for higher performance, lower power, and greater functionality in smaller packages has driven the rapid adoption of 2.5D and 3D Integrated Circuits (ICs). However, the inherent complexity of these multi-die architectures presents significant reliability verification challenges that traditional 2D flows cannot adequately address, particularly concerning electrostatic discha... » read more

Chip Industry Week in Review

By The SE Staff - 06 Feb, 2026 - Comments: 1

Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis

By Siemens EDA - 11 Nov, 2025 - Comments: 0

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

New Frontiers In Fault Detection And Classification

By Laura Peters - 14 Oct, 2025 - Comments: 0

IC manufacturers are increasingly relying on intelligent data processing to prevent downtime, improve yields, and reduce scrap. They are integrating that with fault detection and classification (FDC) to trace faults to their cause. Today’s FDC systems feature better sensors, variability control, and both predictive and prescriptive modeling. In the future, FDC will enable real-time decisio... » read more

Chip Industry Week In Review

By The SE Staff - 26 Sep, 2025 - Comments: 0

U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

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tag: Siemens Digital Industries Software

Chip Industry Week In Review

Shift-left Schematic Memory Contention Analysis

From Billions Of Violations To Actionable Insights: Calibre Vision AI

Enabling A Critical Phase in SoC Development

Extraction Challenges of CFET and Backside Power Delivery

System-level Reliability Verification for 2.5D/3D ICs Using Innovator3D IC and Calibre 3DPERC

Chip Industry Week in Review

Standardization Of HDMs For Hierarchical CDC And RDC Analysis

New Frontiers In Fault Detection And Classification

Chip Industry Week In Review

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