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Week In Review: Design, Low Power


Infineon Technologies acquired Syntronixs Asia, which specializes in precision electroplating, a key process in the assembly process of semiconductors. Syntronixs Asia has a workforce of more than 500 people and has been a major service provider for Infineon since 2009. “Through this acquisition, we have made another important step to strengthen the resilience of our supply chain,” said Tho... » read more

Securing Connected And Autonomous Vehicles


Vehicles are on track to become highly sophisticated Internet of Things (IoT) devices. With the added functionality that connects vehicles to other vehicles, the infrastructure, and even pedestrians, the opportunity for hacking expands. Challenges like complexity and the burden of legacy systems further complicate the situation. The future of connected and autonomous vehicles (CAV) demands leve... » read more

Week In Review: Design, Low Power


Tools Imperas Software released updated simulator and reference models that support the latest RISC-V extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0, plus Privilege Specification 1.12. They are offered both as freely available, open-source reference models for the RISC-V community as well as commercial products. Ansys' multiphysics signoff solutions were... » read more

Zonal Architectures Play Key Role In Vehicle Security


The automotive ecosystem is starting to shift toward zonal architectures, making vehicle functionality less dependent on the underlying hardware and allowing more flexibility in what gets processed where. The impact of that shift is both broad and significant. For carmakers, it could lead to hardware consolidation and more options for failovers in case something goes wrong with any system in... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive The U.S. Congress passed an infrastructure bill that includes mandates for the U.S. automobiles to install technology in new vehicles that will stop impaired drivers from driving a vehicle. Sec. 24220, the advanced impaired driving technology section of the bill says the Secretary of Transportation is responsible for coming up with standards after which the auto industry has at the ... » read more

Week In Review: Design, Low Power


Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day. Tools Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for ... » read more

Partitioning For Better Performance And Power


Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

Hierarchical Verification for EC-FPGA Flow


This document describes the methodology to apply EC-FPGA verification using hierarchical netlists. This approach is recommended in case the verification of the overall design has issues with convergence. The document contains a step-by-step description of different methods while providing reasoning for the soundness of each approach. It is assumed for this document that the reader is familiar w... » read more

Week In Review: Design, Low Power


Tools Cadence's digital and custom/analog flows were certified for TSMC's N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells. Synopsys' digita... » read more

Total Critical Area For Optimizing Test Patterns


Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

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