Week In Review: Design, Low Power


A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Week In Review: Design, Low Power


Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

EDA, IP Revenue Down


EDA and IP revenue dropped 3.1% in Q4 2018 to $2.570 billion, versus $2.652 billion in the same period in 2017, ending a streak of 11 consecutive positive quarters of growth, according to the statistics released today by the Electronic System Design (ESD) Alliance. One quarter doesn't indicate a trend, but it certainly gets everyone's attention after nearly three years of positive news. Now ... » read more

Week In Review: Manufacturing, Test


Trade Trade tensions between the United States and China continue. The U.S. last year slapped a 10% tariff on $200 billion worth of Chinese goods. China retaliated with a 10% tariff on $60 billion of U.S. imports. The U.S. said it wants to increase the tariffs on Chinese goods to 25%, but that action has been postponed. This was the week that the U.S. was supposed to raise tariffs by 25%. I... » read more

Where Electronics Begins, And So Much More


When the Electronic Design Automation Consortium (EDAC) first coined the phrase “Where Electronics Begins” 20 years ago, little did we know how true it is, especially today as we move further into the system-centric era. In those days, EDA tools and methodologies were must-haves for chip designers. The system was only a minor consideration for the EDA community as was the semiconductor supp... » read more

EDA Grabs Bigger Slice Of Chip Market


EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Week In Review: Design, Low Power


M&A QuickLogic acquired SensiML Corporation. Founded in 2017 as a spin-off from Intel, SensiML provides a Software-as-a-Service suite for developing pattern matching sensor algorithms optimized for ultra-low power consumption using machine learning. Details of the deal were not disclosed, though QuickLogic will fund it with shares of common stock. IP CEVA debuted an all-purpose, hybrid... » read more

EDA, IP Show Strong Growth


EDA and IP revenue increased 6.7% worldwide in Q3 2018 to $2.44 billion, compared to $2.28 billion in the same period in 2017. The growth was fueled by rising investments in startups in AI and 5G, as well as a stampede of new and existing companies targeting automotive electrification and autonomous vehicles. While startup funding ultimately will run out as these new markets mature and cons... » read more

Fundamental Shifts In 2018


What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Week In Review: Design, Low Power


Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

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