Week In Review: Design, Low Power


M&A QuickLogic acquired SensiML Corporation. Founded in 2017 as a spin-off from Intel, SensiML provides a Software-as-a-Service suite for developing pattern matching sensor algorithms optimized for ultra-low power consumption using machine learning. Details of the deal were not disclosed, though QuickLogic will fund it with shares of common stock. IP CEVA debuted an all-purpose, hybrid... » read more

EDA, IP Show Strong Growth


EDA and IP revenue increased 6.7% worldwide in Q3 2018 to $2.44 billion, compared to $2.28 billion in the same period in 2017. The growth was fueled by rising investments in startups in AI and 5G, as well as a stampede of new and existing companies targeting automotive electrification and autonomous vehicles. While startup funding ultimately will run out as these new markets mature and cons... » read more

Fundamental Shifts In 2018


What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Week In Review: Design, Low Power


Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

Week In Review: Design, Low Power


Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

EDA, IP Revenues Up Again


EDA and IP revenues were up across the board yet again, buoyed by growth across a number of new markets and an increase in new and existing companies developing chips for those markets. All told, revenue grew to $2.39 billion in Q2 of 2018, an 8.2% increase over the $2.21 billion reported in the same period in 2017, according to numbers released today by the ESD Alliance's Market Statistics ... » read more

Week In Review: Manufacturing, Test


Trade wars It’s difficult to keep up with the U.S.-China trade war. In the latest event, the U.S. Trade Representative (USTR) recently released a 25% tariff on $16 billion in imports from China. This includes 29 tariff lines that represent the heart of the semiconductor industry, according to SEMI. “SEMI, along with hundreds of companies, including Lam Research and KLA-Tencor, submitted wr... » read more

Week In Review: Design, Low Power


Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

Big Shifts In Tech Conferences


By Ed Sperling and Katherine Derbyshire Identifying central themes in technology conferences, or finding enough latitude where the theme is extremely well defined, is becoming challenging throughout the tech industry. Throughout the semiconductor industry, in particular, many are asking how various organizations will differentiate conferences in the future and who will be the target audience... » read more

Week In Review: Design, Low Power


Tools & IP Cadence uncorked the latest version of the Sigrity signal integrity analysis family of tools, adding a 3D design and 3D analysis environment integrated with Allegro PCB tools that allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB for modeling and optimization as one structure. It also adds full Rigid-Flex PCB extraction from... » read more

← Older posts