Blog Review: June 19

Verifying chiplet package connections; CFD plus wind tunnels; regional microelectronics hubs; IoT cybersecurity; LLMs for robots.


Siemens’ John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process.

Cadence’s Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nuanced insights into vehicle performance.

Synopsys’ Ken Potts looks at how the Microelectronics Commons program can help mitigate supply chain risks, address engineering talent shortages, and further advance chip development in the U.S. through a network of eight regional hubs that bring researchers and designers together.

Infineon’s Preeti Khemani checks out the EU’s proposed Cyber Resilience Act, which would mandate cybersecurity requirements for any hardware or software product with digital elements along with the requirement to carry out risk and incident management during the entire product’s lifecycle, or a minimum of 5 years.

Arm’s Chloe Ma explores how multimodal large language models (LLMs) could help robots understand the environment better in a more holistic fashion, adjust movements and actions in response to sensory feedback, and optimize performance across varied and dynamic environments.

Keysight’s Choon-Hin Chang points to in-circuit tests as a way to identify a wide range of common manufacturing defects in PCBAs and introduces several different types of test systems and strategies.

Ansys’ Laura Carter and Kim Hurt find that using simulation throughout various stages of the EV battery cell manufacturing process and production line development can reduce costly trial-and-error experiments and improve up time.

The ESD Alliance’s Bob Smith chats with Maheen Hamid of Breker Verification Systems about why design and EDA define the success of the entire supply chain and warns that without a well-defined design that has been tested for its planned functionalities and is followed by a mapping of the most efficient and economic implementation of the design, the industry cannot scale.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Synopsys’ Keivan Javadi Khasraghi and Ruben Sousa explain why PCIe will continue to be a key player for high-speed interconnects, especially in data centers.

Fraunhofer IIS/EAS’ André Schneider and Martin Lehmann dig into industrial sensors and how innovative strategies can minimize the need for future rework and the risk of failure.

Quadric’s Steve Roddy looks at the new approach to ML networks recently proposed by researchers from MIT and CalTech, known as the Kolmogorov Arnold Network.

Arm’s Vincent Yang examines a method that allows for the extraction of states from registers or latches that are stitched into the scan chains, providing critical diagnostic insights.

Ansys’ Marc Swinnen explains the different classes of AI implementations in the EDA market, where they should be used, and what sort of results to expect from them.

Power architect Barry Pangrle checks out several approaches to silicon health and performance monitoring for SoCs.

Cadence’s Gautam S. shows how PCIe links are poised to take on a role of higher importance in systems as accelerated computing goes mainstream.

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