Designing Ultra Low Power AI Processors


AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

Week In Review: Auto, Security, Pervasive Computing


Synopsys has added nanoscale and macroscale illumination optics to its RSoft Photonic Device Tools version 2020.03. ARVR designers can use the RSoft-LightTools Bidirectional Scattering Distribution Function (BSDF) interface to make interpolated BSDF files for optimized nanoscale and macroscale optics, such as freeform optical prism projectors, eye tracking technologies, and optical planar waveg... » read more

Week In Review: Manufacturing, Test


Chipmakers TrendForce has released its projected foundry rankings in terms of sales for the first quarter. TSMC is still in first place, followed by Samsung, GlobalFoundries and UMC. Samsung has been ramping up chips based on its 7nm logic process using extreme ultraviolet (EUV) lithography. Now, Samsung is ramping up its DRAM devices using EUV and plans to expand its capacity in the arena.... » read more

Week In Review: Design, Low Power


Silicon Labs will acquire Redpine Signals' Wi-Fi and Bluetooth business, development center in Hyderabad, India, and extensive patent portfolio for $308 million in cash. Silicon Labs says the acquisition will expand the company's IoT wireless technology, including smart phone and industrial IoT, and accelerate its roadmap for Wi-Fi 6. The deal is expected to close in the second quarter of 2020.... » read more

Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking


A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

Building A State-of-the-Art Verification Environment


The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

What Worked, What Didn’t In 2019


2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

Week in Review: Iot, Security, Automotive


IoT STMicroelectronics is now supporting LoRaWAN firmware updates over the air (FUOTA) in the STM32Cube ecosystem. Microsoft is adding ANSYS Twin Builder to its Microsoft Azure Digital Twins software, which companies use to create digital twins of machinery and IoT devices that are deployed in remotely. The digital replica of actual devices helps companies predict when maintenance is needed... » read more

Service Revenue Growing With Chip Complexity


Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

Week In Review: Design, Low Power


ANSYS will acquire Dynardo, a provider of simulation process integration and design optimization (PIDO) technology. Dynardo's tools include algorithms for optimization, uncertainty quantification, robustness, scenario variation, sensitivity analysis, simulation workflow building and data mining. Based in Weimar, Germany, Dynardo was founded in 2001 and has been an ANSYS software partner; the ac... » read more

← Older posts