Medical, Industrial & Aerospace IC Design Changes


Medical, industrial and aerospace chips are becoming much more complex as more intelligence is added into these devices, forcing design teams to begin leveraging tools and methodologies that typically have been used only at the leading-edge nodes for commercial applications. But as with automotive, the needs of these systems are changing quickly. In addition to strict quality, safety and sec... » read more

New Architectural Issues Facing Auto Ecosystem


As chips bound for the automotive world move to small process nodes, including 5nm and below, the automotive ecosystem is wrestling with both scaling issues and challenges related to architecting safety-critical systems using fewer chips. This may sound counterintuitive, because one of the main reasons automotive chip providers are moving to smaller nodes is to reduce the number of chips in ... » read more

Speeding Up FPGA Development


Selaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach. » read more

Chip Design Is Getting Squishy


So many variables, uncertainties and new approaches are in play today across the chip industry today that previous rules are looking rather dated. In the past, a handful of large companies or organizations set the rules for the industry and established an industry roadmap. No such roadmap exists today. And while there are efforts underway to create new roadmaps for different industries, inte... » read more

The Challenges Of Building Inferencing Chips


Putting a trained algorithm to work in the field is creating a frenzy of activity across the chip world, spurring designs that range from purpose-built specialty processors and accelerators to more generalized extensions of existing and silicon-proven technologies. What's clear so far is that no single chip architecture has been deemed the go-to solution for inferencing. Machine learning is ... » read more

The Cost Of Programmability


Nothing comes for free, and that is certainly true for the programmable elements in an SoC. But without them we are left with very specific devices that can only be used for one fixed application and cannot be updated. Few complex devices are created that do not have many layers of programmability, but the sizing of those capabilities is becoming more important than in the past. There are... » read more

Hybrid Prototyping


David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Divided On System Partitioning


Building an optimal implementation of a system using a functional description has been an industry goal for a long time, but it has proven to be much more difficult than it sounds. The general idea is to take software designed to run on a processor and to improve performance using various types of alternative hardware. That performance can be specified in various ways and for specific applic... » read more

What Worked, What Didn’t In 2019


2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

Eight Benefits Of Using An FPGA With An On-Chip High-Speed Network


Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. A consequence of this limitation is that designers often spend much of their development... » read more

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