tag: FPGA

Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)
By Technical Paper Link - 05 May, 2026 - Comments: 0

A new technical paper, "Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL," was published by researchers at Barcelona Supercomputing Center. Abstract "The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a ho... » read more

An FPGA-based Accelerator Addressing Bottlenecks in GNN Preprocessing (KAIST et al.)
By Technical Paper Link - 26 Feb, 2026 - Comments: 0

A new technical paper "AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance" was published by researchers at KAIST, Panmnesia, Peking University, Hanyang University, and Pennsylvania State University. Abstract "Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce Au... » read more

AI Starting To Simplify Design Of Programmable Logic
By Liz Allan - 26 Feb, 2026 - Comments: 0

Key Takeaways AI/ML and agentic tools are getting better at helping design and compile FPGAs, but downstream programming is slower to benefit. FPGAs historically have been designed using Verilog or VHDL, but higher-level languages could push more intelligence into compilers. ML tools can also help with mixed-signal co-design by automatically tuning DSP algorithms based on analog simu... » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)
By Technical Paper Link - 15 Feb, 2026 - Comments: 0

TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

HW-Accelerated Physical AI Framework For Resource-Constrained Edge Devices (ASU)
By Technical Paper Link - 07 Jan, 2026 - Comments: 0

A new technical paper titled "Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics" was published by researchers at Arizona State University. Abstract "Physical AI at the edge—enabling autonomous systems to understand and predict real-world dynamics in realtime—demands efficient hardware acceleration. Model recovery (MR), which extracts governing equations ... » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)
By Technical Paper Link - 02 Jan, 2026 - Comments: 0

A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)
By Technical Paper Link - 02 Oct, 2025 - Comments: 0

A new technical paper titled "Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage" was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract "Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices... » read more

The Feasibility Of Deploying FPGA-Based TCEP Synchronization In Real-World Quantum Networks
By Fraunhofer IIS/EAS - 10 Sep, 2025 - Comments: 0

Precise time synchronization is a key challenge in building distributed quantum systems – and it plays a crucial role in secure communications, quantum computing, sensing, the foundations of future 6G networks and the quantum internet. In the paper titled "TCEP-Based Synchronization for Practical Communication Network,"researchers from TU Dresden, IIT Dharwad, Fraunhofer Institute for Inte... » read more

Heterogeneous Multi-Core Architecture Optimizing Power Consumption (TU Dresden)
By Technical Paper Link - 04 Sep, 2025 - Comments: 0

A new technical paper titled "Balancing Power and Performance With Task Dependencies in Multi-Core Systems" was published by researchers at TU Dresden. Abstract "The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. Although power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniq... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 28 Aug, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy