Power Is Limiting Machine Learning Deployments


The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Inferencing Efficiency


Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about how to measure efficiency in inferencing chips, how to achieve the most throughput for the lowest cost, and what the benchmarks really show. » read more

Security’s Very Strange Path To Success


Security at the chip level appears to be heading toward a more promising future. The reason is simple—more people are willing to pay for security than in the past. For the most part, security is like insurance. You don't know it's working until something goes wrong, and you don't necessarily even know right away if there has been a breach. Sometimes it takes years to show up, because it ca... » read more

Disregard Safety And Security At Your Own Peril


Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

5G Design Changes


Mike Fitton, senior director of strategic planning at Achronix, talks with Semiconductor Engineering about the two distinct parts of 5G deployment, how to get a huge amount of data from the core to the edge of a device where it is usable, and how a network on chip can improve the flow of data. » read more

Speeding Up AI


Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to talk about AI, which processors work best where, and different approaches to accelerate performance. SE: How is AI affecting the FPGA business, given the constant changes in algorithms and the proliferation of AI almost everywhere? Blake: As we talk to more and more customers deploying new products and... » read more

How To Integrate An Embedded FPGA


Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Why IP Quality Is So Difficult To Determine


Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

Week In Review: Design, Low Power


M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Chiplet Momentum Builds, Despite Tradeoffs


Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

← Older posts