Higher Performance, Lower Power Everywhere


The future of technology is all about information—not just data—at our fingertips, anywhere and at any time. But making all of this work properly will require massive improvements in both performance and power efficiency. There are several distinct pieces to this picture. One is architectural, which is possibly the simplest to understand, the most technologically challenging to realize, ... » read more

Understanding NI CompactRIO Scan Mode


The LabVIEW Real-Time Module 8.6 introduced powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time th... » read more

Inside UVM, Take Three


The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Why Your FPGA Synthesis Flow Requires Verification


When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Tech Talk: FPGA RTL Checking


Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

New Market Drivers


Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohammed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techn... » read more

The Week In Review: Design


Startup OnScale launched with advanced CAE multi-physics solvers that are seamlessly integrated with a scalable, high performance cloud computing platform built on Amazon's AWS. The company's model is built around a Solver-as-a-Service pay-as-you-go subscription model and targets 5G, IoT/Industrial IoT, biomedical, and autonomous car markets. The company has $3 million in strategic seed fund... » read more

Tech Talk: On-Chip Variation


Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

Bridging Machine Learning’s Divide


There is a growing divide between those researching [getkc id="305" comment="machine learning"] (ML) in the cloud and those trying to perform inferencing using limited resources and power budgets. Researchers are using the most cost-effective hardware available to them, which happens to be GPUs filled with floating point arithmetic units. But this is an untenable solution for embedded infere... » read more

Tech Talk: 5G


Mike Fitton, senior director of strategic planning at Achronix, talks about the new wireless standard, which will make its debut at the Winter Olympics, when it will go mainstream, and what kinds of technical issues need to be addressed to make that happen. https://youtu.be/tUEMKZpbN2Y » read more

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