Why integrating an FPGA chiplet and ASIC die in same package offers flexibility and high performance.
Next-generation SoC platforms are evolving rapidly to process and move enormous amounts of data from the edge; over the network and to the cloud for high data and compute intensive applications such as AI and machine learning, high-performance computing (HPC) and autonomous driving. As a result, next-generation ASICs need to be larger, faster and further optimized for performance, power and area compared to their predecessors. Most importantly, these same platforms need to be flexible to allow for changing standards, evolving algorithms, and reconfigurable processing structures.
Among the spectrum of programmable solutions that include CPUs and GPUs, FPGAs offer the highest compute capacity with the lowest power profile. However, discrete FPGAs functioning as hardware accelerators alongside processors and other compute solutions are expensive and require significant board space for the FPGA plus supporting components. Speedchip FPGA chiplets are a better solution that brings FPGA functionality closer to other system chips, which enables higher bandwidth, reduced system latency, and reduced system cost. Integrating an FPGA chiplet and ASIC die in the same package is an ideal solution for companies looking to bring the programmability and flexibility of an FPGA to their next-generation high-performance system-in-package (SiP) solutions.
Speedchip FPGA chiplets are optimized for embedding in advanced SiP solutions such as 2.5D via silicon interposer or organic substrate. With Speedchip chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Achronix then develops the Speedchip chiplet tailored to the customer’s specification.
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