Stronger, Better Bonding In Advanced Packaging


System-in-package integrators are moving toward copper-to-copper direct bonding between die as the bond pitch goes down, making the solder used to connect devices in a heterogenous package less practical. In thermocompression bonding, protruding copper bumps bond to pads on the underlying substrate. In hybrid bonding, copper pads are inlaid in a dielectric, reducing the risk of oxidation. In... » read more

Wafer Prep Key To Thinning SiP


In its ongoing push to create smaller, thinner, and denser chip packages, the semiconductor industry has intensified its focus on integrating separately manufactured components with different functionalities into systems-in-package (SIPs). Known as heterogeneous integration (HI), this approach now drives the industry’s roadmap for advancement. SiPs enable power-efficient, high-bandwidth conne... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology


Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

LDFO SiP For Wearables & IoT With Heterogeneous Integration


Authors A. Martins*, M. Pinheiro*, A. F. Ferreira*, R. Almeida*, F. Matos*, J. Oliveira*, Eoin O´Toole*, H. M. Santos†, M. C. Monteiro‡, H. Gamboa‡, R. P. Silva* ‡Fraunhofer Portugal AICOS, Porto, Portugal †INESC TEC *AMKOR Technology Portugal, S.A. ABSTRACT The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the require... » read more

Taking Advantage Of Outsourced Test Services


The business model in today’s competitive world of commerce has shifted over recent years to “services.” Companies like Microsoft, Amazon and Google are prime success stories that have advanced the industry with business-enabling services. These economic productivity improvement services allow their customers to focus on product architecture, design and quick time to market. The service p... » read more

Packaging Demands For RF And Microwave


RF and microwave integrated circuits (ICs), monolithic microwave ICs (MMICs) and systems in package (SiPs) are vital for a wide range of applications. These include mobile phones, wireless local-area networks (WLANs), ultra-wideband (UWB), internet-of-things (IoT), GPS and Bluetooth devices. Moreover, RF-optimized packaging products and processes are essential to enabling the 5G ramp-up. RFI... » read more

Protecting Chiplet Architectures With Hardware Security


Chiplets are gaining significant traction as they provide compelling benefits for advancing semiconductor performance, costs, and time to market. With Moore’s Law slowing, building more powerful chips translates into building bigger chips. But with chip dimensions pushing up against reticle limits, growing the size of chips is increasingly impractical. Chiplets offer a new path forward by dis... » read more

What Worked, What Didn’t In 2019


2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

System-in-Package For Heterogeneous Designs


System integration is increasingly being done using 3D packaging technologies rather than integrating everything onto a huge SoC. One motivation is the ability to not just to split up a design in a single process, but to package die from different processes. Sometimes there are economic reasons. Several presentations at HOT CHIPS had a partition of the design into the processor itself, and a... » read more

Is There A Crossover Point For Mainstream Anymore?


Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were being developed at 16/14nm and 10/7nm, it was assumed that developing a chip at 28nm would be less expensive, less complex, and that the process rule deck would shrink. That worked for decades. Th... » read more

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