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All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design


A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more

Cost Characteristics of the 2.5D Chiplet-Based SiP System


A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

Heterogeneous Integration Co-Design Won’t Be Easy


The days of “throwing it over the wall” are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneous integration is the use of advanced packaging technologies to combine smaller, discrete chiplets into one syste... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO


Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs


Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrat... » read more

Enabling The 5G RF Front-End Module Evolution With The DSMBGA Package


The advanced SiP double-sided molded BGA platform has become an industry technology standard in this domain. Applying leading-edge design rules for 3D component placement and double-sided molding, together with conformal and compartmental shielding and in-line RF testing, delivers integration levels in a small form factor with high yield. In addition to formidable SiP capacity and DSMBGA techno... » read more

SiPs And MCMs Broaden Opportunities For Military-Aerospace System Design


Military and aerospace (mil-aero) applications, from satellites and rockets to ships and planes, increasingly require electronic systems and subsystems with high functionality and performance in a small form factor. Meeting these demands poses higher-level challenges for packaging of these microelectronic devices, which needs to be rugged, long-lived, and affordable. Usage of multi-chip modu... » read more

Making More Reliable And More Efficient Auto ICs


Sam Geha, executive vice president of memory solutions at Infineon Technologies, sat down with Semiconductor Engineering to talk about automotive chips, supply chain issues, and integration challenges. What follows are excerpts of that conversation. SE: How do you build an automotive chip that will work in any environment? Geha: The automotive market is, of course, one of the most demand... » read more

Expedera: Custom Deep Learning Accelerators Through Soft-IP


Internet of Things (IoT) and Artificial Intelligence (AI) have caused a massive increase in data generation — and along with it, a need to process data faster and more efficiently. Dubbed a “tsunami of data,” data centers are expected to consume about one-fifth of worldwide energy before 2030. This data explosion is driving a wave of startups looking to gain a foothold in custom accele... » read more

Warpage Of Compression Molded SiP Strips


By Eric Ouyang, Yonghyuk Jeong, JaeMyong Kim, JaePil Kim, OhYoung Kwon, and Michael Liu of JCET; and Susan Lin, Jenn An Wang, Anthony Yang, and Eric Yang of CoreTech System (Moldex3D). Abstract System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing p... » read more

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