Power Reduction In A Constrained World

Why it’s critical to make power a key vector for design convergence.


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement years of leakage reduction.

But the IoT vendors on the planar nodes can’t wait for this to trickle down as they did with the leakage flows. They are implementing power intent and multi-VT schemes that are much more complicated than the wireless devices when these nodes were new. This has squeezed leakage from the designs, making dynamic power front and center. The result: dynamic power differentiation is a pressure across all nodes and end-market spectrums.

With tight constraints on product launches, and human/compute resources, multiple iterations are not an acceptable strategy for dynamic power reduction. It requires a focus throughout the product lifecycle, whether it be stimulus generation, design exploration, implementation, or signoff.

Before writing the RTL, it’s critical to determine how the product will be used, so designers can simulate and emulate power consumption. Without accurate use cases, it’s guesswork where to focus power optimization effort.

During architecture exploration, it is important to explore the solution space. It is far too easy to get trapped in a local minimum, believing the design has optimal power efficiency, without using automation to help with the analysis. High-level synthesis, coupled with RTL synthesis and power estimation, is a key technology for this exploration and validation of the architecture. This allows the fundamental architecture choice to be validated with respect to power, performance, and area.

When transitioning to RTL, inefficient coding practices and fixing bugs can reduce the power efficiency of the design. In the modern SoC design world of dashboards and metrics to drive development, it’s critical to have a formal process to measure power efficiency and make power a key vector for design convergence. RTL power estimation must be tied to synthesis to achieve the accuracy and correlation needed—no one can afford to simply speculate on what will happen—otherwise, you waste resources and time chasing ghosts. The goal isn’t simply to reduce the design’s power—it is to focus on the power improvements with the best return on investment. That ROI includes the power saved, the PPA cost to achieve it and the designer time to explore the tradeoff. This requires deep insight across multiple stimuli, long real-world use models, and across power modes. The integration of RTL power estimation with synthesis is also important to help with the quality of results delivered to place and route. There’s a long tail of dynamic power optimization opportunities that are better suited for an automated tool, as opposed to human coding. Power as a part of the cost function for every phase of synthesis—elaboration, mapping, and optimization—produces the kind of power efficiency gains needed.

During design implementation, it’s important to leverage the same stimulus and activity used in the synthesis stage. You must keep the power under control at this stage.  It is difficult to achieve the same reductions that are possible early in synthesis and architecture exploration.

Leveraging the same peak-power scenarios identified by early RTL power exploration, design signoff should validate the scenario used, and not produce a new surprise. The challenge for power signoff is one of massive compute scale without impacting accuracy or project schedule. This is best achieved through binary-level integration with static timing and implementation.

It is important to cover power at all points in a product’s design and verification life. The biggest opportunities for reduction are in the early phases of the design cycle, using a strong RTL power analysis solution, tightly integrated with synthesis. The use of common engines throughout the flow ensures no late surprises and helps produce the most power efficient end product without requiring extra resources or schedule.

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