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A Full-Stack Domain-Specific Overlay Generation Framework Verified On FPGA


A new technical paper titled "OverGen: Improving FPGA Usability through Domain-specific Overlay Generation" by researchers at UCLA and Chinese Academy of Sciences. "Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and ext... » read more

The End Of Closed EDA


In a previous life, I was a technologist for a large EDA company. One of my primary responsibilities in that position involved talking to a lot of customers to identify their pain points, and what new tools we could develop that would ease their problems. You would think that would be an easy task, but it certainly was not the case. For example, if you ask a developer what their biggest frus... » read more

Designing for FPGA Accelerators


This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

Customizing Processors


The design, verification, and implementation of a processor is the core competence of some companies, but others just want to whip up a small processor as quickly and cheaply as possible. What tools and options exist? Processors range from very small, simple cores that are deeply embedded into products to those operating at the highest possible clock speeds and throughputs in data centers. I... » read more

Heterogeneous Redundant Circuit Design Approaches for FPGAs


New research paper titled "Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs" from researchers at Nagasaki University. Abstract (Partial) "In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach foc... » read more

Toward Democratized IC Design And Customized Computing


Integrated circuit (IC) design is often considered a “black art,” restricted to only those with advanced degrees or years of training in electrical engineering. Given that the semiconductor industry is struggling to expand its workforce, IC design must be rendered more accessible. The benefit of customized computing General-purpose computers are widely used, but their performance improv... » read more

High-Level Synthesis: It’s Still Hardware Design


Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The advantage of using HLS is that it speeds up RTL creation time and reduces verification time by producing bug free RTL quickly from a fully verified C++/SystemC source. The misconception that still exist... » read more

Structural Vs. Functional


When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Software-Hardware Co-Design Becomes Real


For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Formally Verifying SystemC/C++ Designs


We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

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