The Impact of Moore’s Law Ending


Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Power Reduction In A Constrained World


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

Synthesizing Computer Vision Designs To Hardware


Computer vision is one of the hottest markets in electronic design today. Digital processing of images and video with complex algorithms in order to interpret meaning has almost as many applications and markets as there are uses for the human eye. The biggest problem that designers face is that the computer vision system requirements and algorithms change quickly and often. Even the targ... » read more

Accelerate Computer Vision Design Using High-Level Synthesis


Computer vision solutions are all around us, in cars, consumer products, security, retail, and agriculture. But, designing these solutions is not easy, mainly because of constant algorithm upgrades and related requirements changes. This means that wherever the team is in the RTL creation and verification flow, they might have to start over, which can cause an unacceptable delay in the productio... » read more

Could Liquid IP Lead To Better Chips?


Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

The 5G Design Dilemma


Nothing says low power and high performance like an emerging wireless standard that promises to increase link bandwidth, latency, and overall capacity by orders of magnitude while also reducing power. That emerging standard, of course, is 5G. With the number of devices that are projected to use 5G, it’s no surprise that 5G is a strategic initiative for many companies. This explains why des... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Whatever Happened To High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verificati... » read more

Supporting CPUs Plus FPGAs (Part 3)


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

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