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Designing for FPGA Accelerators

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This research paper titled “High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks” was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy).

According to the paper’s abstract, “This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE [design space exploration], and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described.”

Find the technical paper here. Published August 2022.

R. S. Molina, V. Gil-Costa, M. L. Crespo and G. Ramponi, “High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks,” in IEEE Access, 2022, doi: 10.1109/ACCESS.2022.3201107.

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