tag: high-level synthesis

Hardware From Specifications Using AI
By Brian Bailey - 06 May, 2026 - Comments: 0

There is a lot of excitement these days surrounding the idea that AI could make it possible to go from a specification to a design with absolutely no hardware skills. Well, get in line, because this is the umpteenth potential technology that was going to make that possible. Don't get me wrong, it just might do it, but will this be an implementation that is reliable, have decent performance, ... » read more

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)
By Technical Paper Link - 15 Feb, 2026 - Comments: 0

TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

Software-Defined Systems
By Ed Sperling - 26 Jan, 2026 - Comments: 0

Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL
By Vlada Kalinic - 08 Jan, 2026 - Comments: 0

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Formal Verification Of Synthesizable C++/SystemC Designs
By Siemens EDA - 07 Jan, 2026 - Comments: 0

Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL. High-level synthesis (HLS) is a design flow in which design intent is des... » read more

What Does Semiconductor Disruption Look Like?
By Brian Bailey - 25 Sep, 2025 - Comments: 2

When conducting interviews for my article on the incorporation of AI within EDA tools, Anand Thiruvengadam, senior director and head of AI product management at Synopsys, said, "AI has the potential to transform how customers do chip design. The entire EDA flow can be disrupted with AI." He is not alone in making this kind of statement. Each year, I do a predictions piece, and I ask about how A... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)
By Technical Paper Link - 04 Sep, 2025 - Comments: 0

A new technical paper titled "OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs" was published by researchers at Georgia Institute of Technology. Abstract "High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like ... » read more

EDA Startups At DAC 2025
By Jesse Allen - 09 Jul, 2025 - Comments: 0

The 62nd DAC showcased numerous new exhibitors in 2025, including tool and IP providers, design services firms, and component marketplaces. New EDA startups, in particular, had a robust showing, with entrepreneurial engineers seeking to tackle the increasingly complex challenges facing modern chip design with fresh approaches. AI was a strong theme throughout the show, with companies of all ... » read more

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