RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Making Sense Of ML Metrics


Steve Roddy, vice president of products for Arm’s Machine Learning Group, talks with Semiconductor Engineering about what different metrics actually mean, and why they can vary by individual applications and use cases. » read more

Focus Shifts To Wasted Power


Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

Less Margin, More Respins, And New Markets


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

New Challenges In Testing 5G Devices


Alejandro Buritica, senior solutions marketing manager at National Instruments, talks about what will be needed for mass-market testing of 5G devices, how to focus signals to overcome signal attenuation, and how to make over-the-air testing viable where leads are not exposed. » read more

The Great Data Flood Ahead


The number of devices connected to the Internet is expected to exceed 1 trillion devices over the next decade or so. The timeline is a bit fuzzy, in part because no one is actually counting all of these devices, but the implications are pretty clear. A data deluge of biblical proportions is headed our way, and so far no one has any idea of what to do with all of it. From a system-level s... » read more

Open ISAs Gaining Traction


Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

What’s Powering Artificial Intelligence?


While artificial intelligence (AI) and machine learning (ML) applications soar in popularity, many organizations are questioning where ML workloads should be performed. Should they be done on a central processor (CPU), a graphics processor (GPU), or a neural processor (NPU)? The choice most teams are making today will surprise you. To scale artificial intelligence (AI) and machine learning (... » read more

Ensuring A 5G Design Is Viable


Ron Squiers, network solutions specialist at Mentor, a Siemens Business, explains what’s different in 5G chips versus 4G, how to construct a front haul and back haul system so it is testable in the network stack. » read more

Taking Energy Into Account


Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

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