tag: network on chip

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

Efficiency Defines The Future Of Data Movement
By Andy Nightingale - 30 Oct, 2025 - Comments: 0

For decades, chip performance was measured by how much raw compute could be packed onto a die. However, that equation has changed. Moving data across a system-on-chip (SoC) now consumes more energy than the computations it performs. Efficient data movement has become a significant challenge for next-generation SoC designs. AI workloads are multiplying, hyperscale data centers are approaching po... » read more

The Future Of SoC Design Is Data Movement
By Andy Nightingale - 25 Sep, 2025 - Comments: 0

The semiconductor industry is experiencing rapid advances in chiplet adoption, high-bandwidth memory, Compute Express Link (CXL) fabrics, and automotive zonal architectures. As we move into the second half of 2025, the only sustainable path forward is a layered, physically aware, and automated interconnect methodology that can keep pace with escalating complexity. This article is Part Two of... » read more

Benefits And Challenges Of Using Chiplets
By Ed Sperling - 24 Sep, 2025 - Comments: 0

The move to chiplets opens the door to more features than can be packed into a reticle-sized SoC. That potentially means more processing power, simpler designs, and higher yields. But it's not as simple as swapping LEGO blocks into a chassis. Ashley Stevens, director of product management and marketing at Arteris, talks with Semiconductor Engineering about the challenges of using coherent versu... » read more

Inside Chips Podcast: Data Movement In The AI Age
By Ed Sperling - 12 Sep, 2025 - Comments: 0

AI is all about data movement — lots of it. The key is to move data as little as possible, and when it is moved, to do it efficiently, securely, and blindingly fast. Semiconductor Engineering talks with Arteris CEO Charlie Janac in this one-on-one discussion about the impact of AI on networks on chip and what will change going forward. To listen to the podcast, click here. » read more

A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
By Andy Nightingale - 28 Aug, 2025 - Comments: 0

The rise of artificial intelligence (AI) is advancing at breakneck speed, pushing computing demands. At the same time, Moore’s Law slows, making monolithic devices increasingly cost-prohibitive and harder to scale. As traditional monolithic scaling hits the wall, the solution is to disaggregate the design into multiple dies, known as chiplets. These chiplets are mounted on a common substrate ... » read more

Baya Systems: Moving Data Faster
By Ed Sperling And Emma Riverso - 17 Jun, 2025 - Comments: 0

Moving data is one of the big challenges in the AI world. There is so much data being generated that even moving it back and forth from processors to memories requires a significant amount of power, enormous bandwidth, and frequently causes delays that can bog down performance. Now, with substantially more processing, different types of processors on each system on chip (SoC), and the emerging ... » read more

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design
By Arteris - 23 Apr, 2025 - Comments: 0

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Business Challenge • Develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Design Challenges • Ensure different portions ... » read more

Cache Coherence In Network On Chip Design (NTU)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Learning Cache Coherence Traffic for NoC Routing Design" was published by researchers at Nanyang Technological University. "In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time... » read more

Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
By Andy Nightingale - 27 Mar, 2025 - Comments: 0

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases lat... » read more

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