IP Integration Verification At DVClub Europe


Most people involved in pre-silicon verification of digital designs and electronic design automation (EDA) know the folks at Test and Verification Solutions (T&VS – now acquired by Tessolve to offer a full VLSI and test service). Among other things, they organize the Verification Futures (VF) conference in the UK and the DVClub Europe meetings. These are highly technical events, with plen... » read more

Gaps Emerging In System Integration


The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

Enabling Integration Success Using High-Speed SerDes IP


By Niall Sorensen and Malini Narayanammoorthi Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed increases are required to support the bandwidth demands of artificial intelligence (AI), Internet of Things (IoT), virtual reality (VR) and many more ... » read more

What Goes Wrong With IP


Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

Will The Chip Work?


As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?


IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Can IP Integration Be Automated?


What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

Who’s Calling The Shots


Throughout the PC era and well into the mobile phone market, it was semiconductor companies that called the shots while OEMs followed their lead and designed systems around chips. That’s no longer the case. A shift has been underway over the past half decade, and continuing even now, to reverse that trend. The OEM — or systems company as it is more commonly called today — now determine... » read more

Architecting For Optimal Interface IP Integration


Semiconductor Engineering sat down to discuss the design and integration of complex interface [getkc id="43" comment="IP"] with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design at Semtech; and Nav... » read more

IP Market Booms At Advanced Nodes


As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

← Older posts