tag: IP integration

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

System Integration With Standards-Based Automation
By Insaf Meliane - 31 Jul, 2025 - Comments: 0

Today’s semiconductor designs support a broad range of applications, from mobile and edge devices to AI accelerators and data center systems. To keep pace, design teams are shifting from monolithic systems-on-chip (SoCs) to increasingly complex multi-die and chiplet-based architectures. These heterogeneous systems often incorporate IP developed at different times, by different teams, or sourc... » read more

Accelerating IP Reuse
By Ed Sperling - 23 Jul, 2025 - Comments: 0

Semiconductors are no longer monolithic designs developed by a single company. There is more third-party IP from different sources — as many as 1,000 different IPs in a complex SoC — and all of that needs to be integrated and work as one system, something that can require a lot of effort and time. Insaf Meliane, product management and marketing director at Arteris, talks about how the new v... » read more

Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly
By Insaf Meliane - 29 Aug, 2024 - Comments: 0

Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or thousands of IP blocks, leading to significant design challenges. Multi-die architectures, which distribute functional blocks across multiple dice, demand expert planning to ensure connectivity and ... » read more

Physically Aware NoCs
By Ed Sperling - 06 Mar, 2023 - Comments: 0

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

Importance Of Qualifying IP Revisions
By Siddharth Ravikumar - 30 Jan, 2023 - Comments: 0

Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC
By Synopsys - 06 Dec, 2022 - Comments: 0

In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

Raising IP Integration Up A Level
By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Time For FMEDA Reuse?
By Stefano Lorenzini - 07 Jul, 2022 - Comments: 0

How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA. In fact, an FMEDA does not have to be a table; it could be manifested in scripts or some other form, but a table is the easiest way to think of this information. Think of an FMEDA for an IP, as the concept extends easily to a system-on-chip (SoC). T... » read more

Integrating Embedded FPGA Made Easy
By Andy Jaros - 03 Jun, 2021 - Comments: 0

Chip designers have been integrating hard and soft IPs for decades – some being easy to integrate and others much more difficult. But what about eFPGA? It’s a relatively new IP on the IP landscape and according to data from Gartner, the market share of semiconductors with eFPGA is expected to approach $10B in 2023 with greater than 50% compounded annual growth. So, this raises the question ... » read more

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