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Optimizing NoC-Based Designs


Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are re... » read more

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm


Abstract "Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computatio... » read more

End-To-End Traceability


Despite standards such as ISO 26262 and IEC 61508, there are still disconnects and gaps in the supply chain and design-through-manufacturing flows. Kurt Shuler, vice president of marketing at Arteris IP, digs into what's missing, why changes made in one area are not reflected in other areas and throughout the product lifecycle, and why various different phases of the flow don't always match up ... » read more

Reviving The IPO Route For IP Companies


K. Charles Janac, chairman and CEO of Arteris IP, sat down with Semiconductor Engineering to talk about the company's recent decision to go public, including the benefits and risks of operating as a public IP company. SE: The rule of thumb used to be $20 million in revenue was needed for an IP company to do an IPO at the turn of the Millennium, and then it increased to $40 million about a de... » read more

More NoC Wisdom


A common experience for anyone promoting a disruptive technology is that prospective customers understand that what is being offered is different. Still, without a familiar reference to compare, they extrapolate expectations unreliably. Sometimes expectations are extrapolated to infinity: “My existing solution has limitations, but the new technology should have no limitations.” Sometimes ex... » read more

Using Machine Learning For Characterizations Of NoC Components


Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of... » read more

NoC Experiences From The Trenches


Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

Better Optimization For Many-Core AI Chips


The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

Automotive AI Hardware: A New Breed


Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited... » read more

NoCs In Authoritative MPSoC Reference


The MPSoC Forum, sponsored by IEEE and other industry associations, hosts an annual conference in beautiful places around the planet. It is dedicated to showcasing renowned academic and industry experts in multicore and multiprocessor architectures. The goal is to explore trends in system-on-chip (SoC) hardware and software architectures and applications. An additional purpose is to consider th... » read more

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