tag: NoC

Inside Chips Podcast: Data Movement In The AI Age
By Ed Sperling - 12 Sep, 2025 - Comments: 0

AI is all about data movement — lots of it. The key is to move data as little as possible, and when it is moved, to do it efficiently, securely, and blindingly fast. Semiconductor Engineering talks with Arteris CEO Charlie Janac in this one-on-one discussion about the impact of AI on networks on chip and what will change going forward. To listen to the podcast, click here. » read more

A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
By Andy Nightingale - 28 Aug, 2025 - Comments: 0

The rise of artificial intelligence (AI) is advancing at breakneck speed, pushing computing demands. At the same time, Moore’s Law slows, making monolithic devices increasingly cost-prohibitive and harder to scale. As traditional monolithic scaling hits the wall, the solution is to disaggregate the design into multiple dies, known as chiplets. These chiplets are mounted on a common substrate ... » read more

Baya Systems: Moving Data Faster
By Ed Sperling And Emma Riverso - 17 Jun, 2025 - Comments: 0

Moving data is one of the big challenges in the AI world. There is so much data being generated that even moving it back and forth from processors to memories requires a significant amount of power, enormous bandwidth, and frequently causes delays that can bog down performance. Now, with substantially more processing, different types of processors on each system on chip (SoC), and the emerging ... » read more

Cache Coherence In Network On Chip Design (NTU)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Learning Cache Coherence Traffic for NoC Routing Design" was published by researchers at Nanyang Technological University. "In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time... » read more

Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
By Andy Nightingale - 27 Mar, 2025 - Comments: 0

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases lat... » read more

Accelerate And Derisk RISC-V- Based SoC Designs
By Arteris - 26 Mar, 2025 - Comments: 0

How to accelerate and derisk RISC-V-based SoC designs using silicon-proven network-on-chip IP and SoC integration automation software. This technology seamlessly connects any IP from multiple vendors and shortens design cycles and time to revenue. Maximize overall efficiency for the best product design, leveraging the best NoC IP and expert support. Read more here. » read more

Optimizing Data Movement In SoCs And Advanced Packages
By Ed Sperling - 18 Mar, 2025 - Comments: 0

The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

Top 5 Reasons Engineers Need A Smart NoC
By Rick Bye - 27 Feb, 2025 - Comments: 0

As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. The increasing number of IP blocks, often ranging from 50 to more than 500, introduces significant interconnect congestion, timing closure issues, and power dissipation challenges. Additionally, many network-on-chip (NoC) design tasks are s... » read more

Boost SoC Efficiency And Speed With FlexGen Smart NoC IP Automation
By Arteris - 26 Feb, 2025 - Comments: 0

Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arra... » read more

From DIY To Advanced NoC Solutions: The Future Of MCU Design
By Andy Nightingale - 30 Jan, 2025 - Comments: 0

The evolution of microcontrollers (MCUs) has significantly transformed embedded systems, shifting from simple, standalone processors to complex, multifunctional units that rival traditional systems-on-chip (SoCs). These advancements are fueled by the demand for increased computational efficiency, cutting-edge features like AI and machine learning (ML) integration, and the need to address growin... » read more

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