Top Mobile OEM Uses NetSpeed to Boost Its Next Gen Application Processor


The smartphone segment is certainly the most competitive market for chip makers today and the yearly product launch cadence puts a lot of pressure on the application processor design cycle. End-users expect to benefit from higher image definition, better sound quality, ever faster and more complex applications which push the limits of application processor performance in terms of higher frequen... » read more

Automating Front-End SoC Design With NetSpeed’s On-Chip-Network IP


This white paper from The Linley Group examines the challenges of turning SoC architecture specifications into successful design implementations. It presents the case that SoCs are becoming too large and complex for existing design methodologies and identifies the need for a more automated front-end design process. To read more, click here. » read more

Why Is Semiconductor Schedule Predictability Boring?


Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top en... » read more

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs


The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP


Solid state storage is rapidly supplanting rotary storage in data center computing, driven by the competing needs for lower power consumption, lower latency and higher bandwidth. But the inherent unreliability of flash cells mandates the use of sophisticated host controllers to guarantee data reliability and endurance for enterprise solid state disks (SSD). Leading enterprise SSD companies have... » read more

How To Reduce Timing Closure Headaches


As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

On-Chip Networks Optimize Shared Memory For Multicore SoCs


Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput. For more information, click here. » read more

Top 5 Reasons The SoC Interconnect Matters


The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

NoC Versus PIN: Size Matters


Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC archi... » read more

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations


When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the G... » read more

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