tag: system on chip

Designing for FPGA Accelerators
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

A Holistic Approach To Energy-Efficient System-On-Chip (SoC) Design
By Synopsys - 10 May, 2022 - Comments: 0

It takes a great deal of energy to power the modern world, and demand grows every day. This is especially true for electronics, where ever increasing automation and more intelligent devices incessantly demand more power. Many applications that use chips face a variety of pressures for reduced power consumption and better energy efficiency. In response, the semiconductor and electronic design au... » read more

Where Do Memory Maps Come From?
By Guillaume Boillet - 03 Mar, 2022 - Comments: 0

A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life. T... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

Hyper-Convergence Is The New Normal For Digital Implementation
By Yudhan Rajoo - 23 Sep, 2021 - Comments: 0

The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

FPGA Prototyping: Supersizing Scale And Performance
By Synopsys - 11 May, 2021 - Comments: 0

Given the cost of re-spinning a system-on-chip (SoC), semiconductor companies have always looked for ways to verify and validate the SoC before tape-out. Prototyping using field programmable gate arrays (FPGAs) became a key methodology as part of this pre-silicon verification and validation effort. Click here to read more. » read more

The Challenge Of Fitting In
By Ann Mutschler - 30 Nov, 2015 - Comments: 0

Connections between players in the semiconductor industry are becoming critical for survival. Whether the focus is a connected car, home automation, health care or the energy grid, each company in each of those markets relies on others to build useful products. There are several forces at work here. One is an emphasis on connecting everything, regardless of whether it is inside a single vert... » read more

SoC Verification Made Easy With Aldec HES-DVM
By Aldec - 23 Sep, 2015 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document... » read more

RTL Design-For-Power Methodology
By Various Writers - 14 Feb, 2013 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

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