Energy efficiency through the system-on-chip (SoC) design flow, from architecture to signoff.
It takes a great deal of energy to power the modern world, and demand grows every day. This is especially true for electronics, where ever increasing automation and more intelligent devices incessantly demand more power. Many applications that use chips face a variety of pressures for reduced power consumption and better energy efficiency. In response, the semiconductor and electronic design automation (EDA) industries have developed a wide range of techniques to meet these requirements. This white paper provides some background on the problem, describes some of the available technologies to help and presents a holistic solution for energy efficiency through the system-on-chip (SoC) design flow, from architecture to signoff.
Drivers of Energy Demand
In the simplest terms, more electronic devices require more power to operate. In the last several decades, almost every aspect of daily life has evolved to rely more on electronic gadgets backed by massive data and storage centers. Naturally, demand is growing, but…
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Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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