GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)


A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

MTJ-Based CRAM Array


A new technical paper titled "Experimental demonstration of magnetic tunnel junction-based computational random-access memory" was published by researchers at University of Minnesota and University of Arizona, Tucson. Abstract "The conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence because ... » read more

Efficient Electronics


Attention nowadays has turned to the energy consumption of systems that run on electricity. At the moment, the discussion is focused on electricity consumption in data centers: if this continues to rise at its current rate, it will account for a significant proportion of global electricity consumption in the future. Yet there are other, less visible electricity consumers whose power needs are a... » read more

Optimizing Energy At The System Level


Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

Re-architecting Hardware For Energy


A lot of effort has gone into the power optimization of a system based on the RTL created, but that represents a small fraction of the possible power and energy that could be saved. The industry's desire to move to denser systems is being constrained by heat, so there is an increasing focus on re-architecting systems to reduce the energy consumed per useful function performed. Making signifi... » read more

Increasing AI Energy Efficiency With Compute In Memory


Skyrocketing AI compute workloads and fixed power budgets are forcing chip and system architects to take a much harder look at compute in memory (CIM), which until recently was considered little more than a science project. CIM solves two problems. First, it takes more energy to move data back and forth between memory and processor than to actually process it. And second, there is so much da... » read more

Energy Usage in Layers Of Computing (SLAC)


A technical paper titled “Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining” was published by researchers at SLAC National Laboratory and Stanford University. Abstract: "Estimates of energy usage in layers of computing from devices to algorithms have bee... » read more

A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters


A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

Impact of Semiconductor Optical Amplifers On Performance & Power Consumption in Data Centers (UCSB)


A new technical paper titled "Integrated SOAs enable energy-efficient intra-data center coherent links" was published by researchers at UC Santa Barbara. "In this work, we analyze the impact of integrated semiconductor optical amplifiers (SOAs) on link performance and power consumption, and describe the optimal design spaces for low-cost and energy-efficient coherent links. Placing SOAs afte... » read more

Digital Neuromorphic Processor: Algorithm-HW Co-design (imec / KU Leuven)


A technical paper titled "Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design" was published by researchers at imec and KU Leuven. "In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architect... » read more

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