Does System Design Still Need Abstraction?


About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) seemed complete with logic synthesis becoming well-adopted. The next step seemed to be so obvious at the time: High-level synthesis (HLS) and transaction-based development beyond RTL—also taking into ... » read more

Accelerating Toshiba’s Advanced System-on-Chip (SoC) Design with Synopsys’ Fusion Compiler


Authors: Mitchy M. Mitsuyasu, Senior Specialist, Semiconductor R&D, Toshiba Electronic Device & Storage Corp.; Akira Nikaido, Director Product Marketing, Synopsys. Toshiba Electronic Devices & Storage Corporation, part of the broader Toshiba, Kawasaki Japan, has long been a technology leader in Advanced SoCs spanning multiple, key market verticals. This includes automotive, communications, I... » read more

Opposites Attract: IP Standardization vs. Customization


Have you had a look lately at an autonomous driving SoC? Have you noticed, besides the cool machine learning stuff, the grocery list of third-party IP that goes into it? It is a long, long list, composed of pieces both big and small and quite diverse. For example, interface and peripheral PHYs and controllers, memories, on-chip interconnects, PVT monitors and PLLs. In some highly-publicized exa... » read more

Challenges To Building Level 5 Automotive Chips


It’s an exciting time in the automotive space, and this is especially true when it comes to all of the activity around autonomous driving and the path to achieving full Level 5 autonomy. The technology is complex, the ecosystem seems to get more complex by the day, and simulating autonomous systems safely makes this an extremely fascinating area from an engineering perspective. At the heart o... » read more

A Complete System-Level Security Verification Methodology


Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

The Power Of Virtual Prototyping


As embedded SoCs continue to become more powerful and complex, beating the market may very well rely on non-traditional approaches to product design and development. Software-based methodologies involving virtual prototypes are helping to prove out designs earlier and enable companies to parallelize hardware and software development. Click here to download PDF. » read more

SOC Design & IP Management—A Must For Functional Verification


As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler


This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

Quantifying the Value of On-Chip Debug


White paper authored by Semico Research, quantifies the benefits of using on-chip debug and monitoring technology, specifically UltraSoc's technology. Rising design complexityIn the last several years, contemporary SoCs (system-on-a-chip) have become increasingly complex. They now consist of 100s of millions of gates, 100 or more discrete semiconductor intellectual property (SIP) blocks, hi... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

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