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SoC Verification From Pre-Fabrication To The Over-the-Air Update


The recent new of attacks on system infrastructures serves to highlight that hardware vulnerabilities in the supply chain are not only possible but inevitable if proper precautions are ignored. Verification throughout the entire supply chain is necessary to ensure the safety and security of hardware. Starting as early as the pre-fabrication stage, vulnerabilities, if left unchecked, can be an o... » read more

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance


Paper presented by Sergio Marchese & John Hallman of OneSpin Solutions & The Aerospace Corporation. Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available ... » read more

Using Formal To Verify Safety-Critical Hardware For ISO 26262


Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. These sophisticated features are made possible by increasingly complex electronic systems—systems that... » read more

Trust Assurance And Security Verification Of Semiconductor IPs And ICs


Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust an... » read more

Formal Solutions For SystemC/C++ Verification


OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

Shifting The Burden Of Tool Safety Compliance From Users To Vendors


Functional safety standards demand that this risk be assessed and adequately minimized through tool qualification and other processes. For engineering teams, this is a time-consuming task and, worryingly, one for which there are no mature solutions yet. Tool vendors may provide safety certificates or packages, in an attempt to support their customers with safety compliance. Strategies... » read more

Formal Verification Of Floating-Point Hardware With Assertion-Based VIP


Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the ... » read more

Trust Assurance And Security Verification of Semiconductor IPs And ICs


Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust... » read more

ISO 26262:2018 Fault Analysis In Safety Mechanisms


Authors: Jörg Grosse1, Mark Hampton1, Sergio Marchese1, Jörg Koch2, Neil Rattray1, Alin Zagardan2 1OneSpin Solutions, Munich, Germany 2Renesas Electronics Europe, Duesseldorf, Germany ISO 26262-5 requires the determination of hardware safety metrics, including SPFM and LFM. Latent and residual diagnostic coverage are also important metrics to assess the effectiveness of safety mechanisms... » read more

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation


Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively. Simulation-based verification, on the other hand, requires significantly more effort while providing a fraction of the coverage. However, chip complexity is rapidly increasing. ASICs and FPGAs for heterogeneous c... » read more

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