Author's Latest Posts

Hierarchical Verification for EC-FPGA Flow

This document describes the methodology to apply EC-FPGA verification using hierarchical netlists. This approach is recommended in case the verification of the overall design has issues with convergence. The document contains a step-by-step description of different methods while providing reasoning for the soundness of each approach. It is assumed for this document that the reader is familiar w... » read more

Beyond Bug Hunting: Verification Coverage From Safety To Certification

Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Co... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores

Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

SoC Verification From Pre-Fabrication To The Over-the-Air Update

The recent new of attacks on system infrastructures serves to highlight that hardware vulnerabilities in the supply chain are not only possible but inevitable if proper precautions are ignored. Verification throughout the entire supply chain is necessary to ensure the safety and security of hardware. Starting as early as the pre-fabrication stage, vulnerabilities, if left unchecked, can be an o... » read more

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance

Paper presented by Sergio Marchese & John Hallman of OneSpin Solutions & The Aerospace Corporation. Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available ... » read more

Using Formal To Verify Safety-Critical Hardware For ISO 26262

Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. These sophisticated features are made possible by increasingly complex electronic systems—systems that... » read more

Trust Assurance And Security Verification Of Semiconductor IPs And ICs

Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust an... » read more

Formal Solutions For SystemC/C++ Verification

OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

Shifting The Burden Of Tool Safety Compliance From Users To Vendors

Functional safety standards demand that this risk be assessed and adequately minimized through tool qualification and other processes. For engineering teams, this is a time-consuming task and, worryingly, one for which there are no mature solutions yet. Tool vendors may provide safety certificates or packages, in an attempt to support their customers with safety compliance. Strategies... » read more

Formal Verification Of Floating-Point Hardware With Assertion-Based VIP

Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the ... » read more

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