Variables Complicate Safety-Critical Device Verification


The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Real Highlights For Virtual DAC 2020


My first time at DAC was in 2006 in San Francisco. I was mesmerized by it: so many people, so much cool technology, so much fun with weird giveaways, raffles, happy hours, the Denali party and Disco Inferno at the legendary Fillmore. DAC is the most important, comprehensive conference for anyone developing integrated circuits (ICs) and systems-on-chips (SoCs). With an incredible list of ... » read more

Trust Assurance And Security Verification of Semiconductor IPs And ICs


Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust... » read more

Why It’s So Hard To Create New Processors


The introduction, and initial success, of the RISC-V processor ISA has reignited interest in the design of custom processors, but the industry is now grappling with how to verify them. The expertise and tools that were once in the market have been consolidated into the hands of the few companies that have been shipping processor chips or IP cores over the past 20 years. Verification of a pro... » read more

Keep The Wooden Horse Out Of Your Chip


The OneSpin's Holiday Puzzle tradition has reached its fourth year: hear, hear! In December 2016, OneSpin challenged engineers to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. The OneSpin 2018-19 Holiday Puzzle asked engineers to desi... » read more

Week In Review: IoT, Security, Auto


Internet of Things SiFive is bringing RISC-V to IoT makers and university developers through the RISC-V-based SiFive Learn Initiative, an open-source learning package that can be used to create a low-cost RISC-V hardware compatible with AWS IoT Core. The development platform SiFive Learn Inventor has a software package and education enablement course. It includes: The programmable SiFive Lear... » read more

ISO 26262:2018 Fault Analysis In Safety Mechanisms


Authors: Jörg Grosse1, Mark Hampton1, Sergio Marchese1, Jörg Koch2, Neil Rattray1, Alin Zagardan2 1OneSpin Solutions, Munich, Germany 2Renesas Electronics Europe, Duesseldorf, Germany ISO 26262-5 requires the determination of hardware safety metrics, including SPFM and LFM. Latent and residual diagnostic coverage are also important metrics to assess the effectiveness of safety mechanisms... » read more

A Glossary For Chip And Semiconductor IP Security And Trust


A significant portion of electronic system vulnerabilities involves hardware. In 2015 the Common Vulnerabilities and Exposures (CVE-MITRE) database recorded 6,488 vulnerabilities. A considerable proportion (43%) can be classified as software-assisted hardware vulnerabilities (see Fig. 1). The discovery of Meltdown and Spectre in January 2018 has sparked a series of investigations into hardware ... » read more

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation


Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively. Simulation-based verification, on the other hand, requires significantly more effort while providing a fraction of the coverage. However, chip complexity is rapidly increasing. ASICs and FPGAs for heterogeneous c... » read more

Synthesizing Hardware From Software


The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

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