Week In Review: Design, Low Power

HBM3-ready subsystem; RF SOI switch reference design flow; MIPI DSI-2 v2.0; IoT security research.


Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools tuned for Tower’s CMOS, BiCMOS, SOI and Silicon Germanium (SiGe) process technologies.

Synopsys reported third quarter 2021 financial results with revenue of $1,057.1 million, up 9.7% from the same quarter last year. The company is substantially raising fiscal 2021 targets, said Synopsys chairman and co-CEO Aart de Geus. “As we look to next year and beyond, we are aiming at crossing $5 billion in revenue by 2023, with double-digit annual revenue growth and continuing margin expansion.”

Picocom deployed Cadence’s Palladium Enterprise Emulation Platform to accelerate the verification and pre-silicon software validation of its SoC designs for 5G open radio access network (RAN) applications. Picocom said it achieved faster hardware and software integration, citing an emulation speedup of 1000X when compared with RTL simulation. The company also used a range of other Cadence tools for power analysis and interface testing.

Rambus completed its acquisition of PLDA, adding CXL 2.0, PCIe 5.0 and PCIe 6.0 controller and switch IP. “CXL and PCIe are critical enablers for next-generation data centers that will deliver the high-speed interconnects needed to tackle demanding workloads in AI/ML and HPC applications,” said Luc Seraphin, president and CEO of Rambus. “The addition of PLDA’s world-class digital IP and engineering expertise accelerates our roadmap and expands our market opportunity, and we are excited to welcome them to the team.”

Rambus debuted a HBM3-ready memory interface subsystem consisting of a fully-integrated PHY and digital controller. It supports data rates of up to 8.4 Gbps, can deliver over a terabyte per second of bandwidth, and has a built-in hardware-level performance activity monitor. The IP license also includes 2.5D package and interposer reference designs.

The MIPI Alliance published version 2.0 of the MIPI Display Serial Interface 2 specification. MIPI DSI-2 v2.0 includes updates to the user experience and improved power savings, as well as offering twice the bandwidth of the previous version when coupled with the most recent MIPI C-PHY and D-PHY interfaces. New features include the ability to transition between a variety of modes such as high resolution and frame rate to low latency GUI and static modes. It also includes support for the latest VESA Display Stream Compression (VESA DSC) 1.2b and VESA Display Compression-M (VDC-M) 1.2 codecs.

Arasan Chip Systems released the second generation of its Sureboot QSPI NOR Flash memory controller IP. An extended version of the SPI protocol allowing the use of 4 data lanes, it provides immediate access to flash memory from SPI mode on startup, or alternatively it can be configured for any other mode from SPI to Dual SPI or Quad SPI.  Additionally, a DMA command may be issued to copy memory from the flash device to anywhere else on the bus.

Infineon is coordinating a research project with the goal of improving security for IoT devices. The “Design methods and hardware/software co-verification for the unique identifiability of electronic components” (VE-VIDES) project includes twelve partners from the research and academic sectors as well as from electronics and end user industries working to systematically identify potential security gaps in the design phase and to use automatically generated, trustworthy mechanisms to protect electronic systems against attack. Also participating in the project is CARIAD, Fraunhofer IIS EAS, IMMS, OFFIS, OneSpin, Robert Bosch, Siemens, Synopsys, Chemnitz University of Technology, Ulm University, and X-FAB. The project is supported by the German Federal Ministry of Education and Research.

TechInsights acquired VLSI Research, a provider of market research and economic analysis covering the semiconductor supply chain. “When I first learned TechInsights wanted to bring us together, it was clear there was a unique opportunity to connect market and technical analysis on high-volume and emerging applications of technology in ways that has never been done before” said G. Dan Hutcheson, Chairman and CEO of VLSI Research. “Merging both into a single platform would offer the industry a powerful new way to view the past, present and future of the semiconductor sector.” VLSI Research was founded in 1976.

HPC & quantum
Xanadu, a full-stack photonic quantum computing startup, is partnering with Imec to develop and fabricate photonic qubits based on ultra-low loss silicon nitride (SiN) waveguides. Imec’s wafer-scale low loss SiN photonics platform was initially developed for communications applications. Xanadu claims its approach, which uses silicon nitride to generate ‘squeezed states’ that create qubits, can scale to one million qubits with fault tolerance.

Construction of the first quantum computer in the United Arab Emirates is underway, according to The Quantum Daily and UAE newspaper The National. Built by the Technology Innovation Institute’s Quantum Research Centre, it is based on superconducting qubit technology (similar to that used by IBM and Google). Researchers plan to use the quantum computer for investigating AI, drug discovery, navigation, and cryptography. It will be based in Abu Dhabi.

Researchers at the Graubünden University of Applied Sciences in Switzerland set a new record by calculating the length of π to 62.8 trillion digits, besting the previous record by about 12.8 trillion digits. The calculation took the university’s HPC system, equipped with a terabyte of memory, a pair of AMD Epyc 7542 CPUs, and 38 16TB hard drives, 108 days. The ten last known digits of Pi are now 7817924264.

The U.S. Department of Energy will provide $6 million in funding for five R&D projects aimed at applying 5G networks to scientific purposes. “Telecommunication networks based on 5G technologies have the potential to transform how we design, build, operate, and optimize scientific facilities and experiments,” said Barbara Helland, Associate Director of Science for Advanced Scientific Computing Research. “Advanced wireless networks will make scientific facilities more mobile and agile, while creating a pathway to the development of new sensing instrumentation for the collection of data in remote, inaccessible locations.”

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