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Will The Fitbit Charge 5 Outshine The Fitbit Luxe?


We don’t know, and we do not comment on whether one device is better than its previous generation. What we do is look at and compare generations of devices. And while we wait for our pre-order of our Fitbit Charge 5 to arrive, we will take a look at what Fitbit Luxe has inside of it. Fig. 1: Fitbit Luxe. Fig. 2: Fitbit Inspire 2. The Luxe has other changes from the Inspire 2, inc... » read more

Week In Review: Design, Low Power


Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Micron B47R 3D CTF CuA NAND Die, World’s First 176L (195T)


Micron’s 176L 3D NAND is the world’s first 176L 3D NAND Flash memory. TechInsights just found the 512Gb 176L die (B47R die markings) and quickly viewed its process, structure, and die design. Micron 176L 3D NAND is one of the most groundbreaking technologies to date, and it is especially for the storage application such as data center, 5G, AI, cloud, intelligent edge, and mobile devices. Mi... » read more

Micron D1α, The Most Advanced Node Yet On DRAM


Finally, we got to see D1α DRAM generation! It’s 14nm! After a quick viewing of the Micron D1α die (die markings: Z41C) and its cell design, we have determined its actual technology node (design rule), in contrast to the claims of market literature. It is the most advanced technology node ever on DRAM, and it is the first sub-15nm cell integrated DRAM product. The Micron Z41C die removed... » read more

Scaling CMOS Image Sensors


After a period of record growth, the CMOS image sensor market is beginning to face some new and unforeseen challenges. CMOS image sensors provide the camera functions in smartphones and other products, but now they are facing scaling and related manufacturing issues in the fab. And like all chip products, image sensors are seeing slower growth amid the coronavirus outbreak. Manufactured a... » read more

What Is DRAM’s Future?


Memory — and DRAM in particular — has moved into the spotlight as it finds itself in the critical path to greater system performance. This isn't the first time DRAM has been the center of attention involving performance. The problem is that not everything progresses at the same rate, creating serial bottlenecks in everything from processor performance to transistor design, and even the t... » read more

What’s Next For High Bandwidth Memory


A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

DRAM Scaling Challenges Grow


DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

Week In Review: Manufacturing, Test


Chipmakers In its latest move to cut costs and focus on its core business, GlobalFoundries (GF) has announced plans to jettison its U.S. photomask operations in Burlington, Vt., but the foundry vendor will maintain a stake in its joint venture mask unit. Under the plan, Toppan Photomasks will acquire certain assets of GF’s Burlington photomask facility. “GF is transferring its mask tool... » read more

Advanced Patterning Techniques For 3D NAND Devices


By Yu De Chen and Jacky Huang Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At th... » read more

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