Chiplet Planning Kicks Into High Gear


Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve... » read more

Designing For In-Circuit Monitors


In every application space the semiconductor ecosystem touches, in-circuit monitors and sensors are playing an increasing role in silicon lifecycle management and concepts around reliability and resiliency — both during design as well as in the field. The combination of true system-level design, in/on-chip monitors, and improved data analysis are expected to drastically improve reliability... » read more

Startup Funding: October 2022


Investors poured $3.5 billion into 113 startup companies in October 2022, especially new battery technology, AI hardware, and faster memory access. Battery technology dominated the fundraising in October thanks to the U.S. Department of Energy and four funding rounds that exceeded $200M. The DOE awarded sizeable grants to help 20 companies, including six startups, build out battery material ... » read more

Startup Funding: April 2022


Silicon photonics holds the potential to vastly increase bandwidth in chips and systems while reducing power use — and investors are taking note. In April, one of the largest funding rounds went to a startup developing chip-to-chip optical I/O. But that wasn't all. Photonics funding showed up in AI with a photonic Tensor core, in room-temperature quantum computing, and, of course, in lidar an... » read more

The Gargantuan 5G Chip Challenge


Blazing fast upload and download speeds for cellular data are coming, but making the technology function as expected throughout its expected lifetime is an enormous challenge that will require substantial changes across the entire chip ecosystem. While sub-6GHz is an evolutionary step from 4G LTE, the real promise of 5G kicks in with millimeter-wave (mmWave) technology. But these higher-freq... » read more

Week In Review: Design, Low Power


Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Week In Review: Design, Low Power


Arteris IP will acquire the assets of Magillem Design Services, combining Arteris' NoC interconnect IP with Magillem's chip design and assembly environment. Magillem’s software products will continue to be offered separately from the Arteris interconnect IP offerings and the joined company will continue to execute on Magillem’s existing product and technology roadmaps. Substantially all Mag... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Synopsys’ Cybersecurity Research Center disclosed that its research resulted in three Common Vulnerability and Exposures (CVE) advisories on wireless router chipsets that have partial authentication bypass vulnerabilities. The vulnerability lets an attacker send an unencrypted data frame through a WPA2-protected WLAN, which will may respond with an encrypted data frame that the atta... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Many IoT devices have some of the 19 bugs known as Ripple20 vulnerabilities. Researchers JSOF discovered the security flaws in library produces by Treck, Inc., which is used in many IoT devices. Edge, cloud, data center Rambus delivered its 112G XSR/USR PHY IP on TSMC 7nm process (N7). The SerDes PHY was designed for chiplets and co-packaged optics (CPO) architectures that are des... » read more

Week In Review: Design, Low Power


Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

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